How to Process the Backside of GaAs Wafers
Costas Varmazis, Gerald S. D''Urso, Henry Hendriks Process Engineering Group, M/A-COM Inc., Lowell, Mass. -- Semiconductor International, 12/1/2000
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At a Glance | | |
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One major challenge in expanding wafer fab capacity lies in backside processing. Historically, most GaAs backside wafer process steps have been very labor-intensive because there has not been much available in manufacturing equipment to support them. Yield has often depended on the skill of experienced technicians. A number of backside process steps must be changed and automated to significantly increase throughput capacity. GaAs fab process engineers must work closely with equipment suppliers to develop and qualify new capital equipment for backside automation capability that will enable further increases in capacity.
Following, we present an overview of the process steps involved in backside processing for GaAs wafers with through via holes. Figure 1 shows a cross-sectional view of the major steps as the wafer is processed. The following steps are performed after completion of final front-side dc electrical test.
The wafers are mounted onto flat carriers with a thermoplastic mounting medium or high-temperature wax.1-4 The most widely used flat carriers are made from sapphire, which is thermally rugged, resistant to most wet chemical etch solutions, and can be machined to an optically flat surface.
| 1. Backside processing steps for GaAs wafers with through via holes. |
The photoresist mask is stripped from the backside wafer surfaces by first immersing the wafers in a basic photoresist stripping solution, followed by exposure to a high-oxygen plasma environment.8 Depending on the aggressiveness of the photoresist mask post-bake and the via hole etch conditions, the stripping solution may need to be either sprayed onto the backside wafer surfaces or heated and agitated. However, the wet stripping solution step can result in premature erosion of the mounting medium. If a wet spray strip technique cannot be utilized, a high-oxygen-content RIE can be used to totally remove the remaining residual photoresist and organics from the backside wafer surfaces prior to seed layer deposition.
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| 2. Rough grinding is usually employed in high-volume applications. It is followed by polishing or spray etching to remove the residual grinding damage. |
For electroless plating, Pd/Au18,28-31 or Pd/Ni32 is used where Pd acts as a catalyst for the subsequent electroless plating of Au or Ni. A thick electroplated Au layer is then deposited onto the seed layer.8,16,25,28 The electroplated Au must be thick enough to meet thermal conductivity requirements and improve the mechanical strength of the thinned wafer.28 If a Au-Sn eutectic solder die attach process is subsequently used, the layer must be thick enough to accommodate leaching of some gold during eutectic solder die attach so voiding can be minimized.8 A batch or cluster sputter deposition tool for the seed layer is amenable to high-volume manufacturing and therefore is widely used by most GaAs fabs.
| 3. Batch RIE tools are widely used to etch the via holes. |
If the die are to be attached to ceramic packages using Au-Sn eutectic solder, then a solder "stop" metal layer such as Ti, Ni or Cr that readily oxidizes needs to be deposited inside the vias to prevent solder from "wicking up" and "blowing out" the front-side metal pads.30 If the die are to be attached using a conductive epoxy, then a solder stop layer is unnecessary. A photolithography/wet etch process is typically used to clear the solder stop metal layer from the backside metal plane to minimize voiding at the back-metal planar surface during the eutectic solder die attach step.
If the wafers are to be diced by scribing (Fig. 5), then backside street grids need to be defined by using a photolithography/wet etch process.8,33 If the wafers are to be diced by sawing, the backside grids can be implemented to reduce yield loss from sawing through the soft gold layer.8,33 It is possible to combine the photolithography steps for solder stop and backside street grid by using one contact mask alignment for backside street grid and a flood exposure followed by a develop step to clear the thick positive photoresist layer from the backmetal surface.
| 4. Electroless plating is often used to deposit the seed layer needed for electroplating. |
At both inspect and rf test, computer maps are generated to distinguish acceptable die from poor visual and/or electrical die. These maps are fed and combined in an automatic die poking system.8 The thinned wafer is mounted onto dicing tape and either scribed or sawn.8,34 An automatic die poking system uses the maps to pick and place the acceptable die into gel-packs.
| 5. Wafers are diced by scribing. |
New refinements
Several backside fab process steps for wafers with via holes have recently been changed at M/A-COM's fab in Lowell, Mass., to increase throughput capacity and improve yield. First, the mounting medium was changed from wax, which was diluted in trichloroethylene (TCE), to a thermoplastic adhesive. The thermoplastic adhesive has a much higher flow temperature than the wax, which allowed for the increase of the photoresist mask post-bake temperature and a significant decrease in post-bake time. Second, a semi-automatic vacuum wafer mounting system was purchased and qualified to replace an old vacuum oven and some custom wafer mounting fixtures. Third, the solvent cleaning bath process for dismounted wafers was changed from heated TCE, a suspected carcinogen, and room-temperature acetone to ATMI Vapure 200, an acetone replacement solution that is slightly more expensive than acetone.
A backside street grid process using a thick positive photoresist mask to first define the streets and then protect the solder-stop nickel within the via holes was implemented. After the backside street grids are defined, a flood exposure and develop process is done to clear the photoresist from the backside plane. Significant time is saved by using two exposures with one photoresist mask.
New batch and cluster configuration sputtering systems are being evaluated along with wafer plating systems for the seed and gold layer depositions. Cross contamination between sputter targets is being evaluated for batch systems because both frontside and backside sputter processes are expected to be done in the same system. Cross target contamination is not an issue for cluster tools, but these tools are much more expensive than a batch system. Cassette-to-cassette wafer handling may need to accommodate both regular wafers for frontside and thinned wafers mounted on carriers for backside sputter process steps.
A more anisotropic, higher bias via RIE process has been developed to reduce the via hole size to fit within smaller frontside metal ground pads. However, the temperatures of both photoresist mask hard bake and the photoresist stripping bath had to be increased. Also, the solder-stop etch photomask spin conditions had to be changed to make sure that thick positive photoresist flowed into and covered the smaller via holes. •
Costas Varmazis is distinguished fellow of technology and process engineering manager in M/A-COM’s GaAs operations. He has a Ph.D. in solid-state science and engineering from Columbia University (New York). He did postdoctoral work in superconductivity at Brookhaven National Laboratory (Upton, N.Y.) and at the State University of New York at Stony Brook, and later was a professor of applied physics at the University of Crete (Greece). He has been with M/A-COM since 1984, involved in developing processes used to manufacture MMICs.Gerald S. D’Urso is a senior reliability engineer at M/A-COM Engineering and Technology Group. He has been involved with GaAs and silicon wafer processing for M/A-COM since 1979, working on a number of programs related to wafer manufacturing and process/product development. D’Urso received a B.S.E.T. from Northeastern University (Boston) in 1988. He joined the M/A-COM Corporate Reliability Group in 1996.
Henry Hendriks is a senior process engineer at the M/A-COM GaAs wafer fab. He received a B.S. in materials science from Cornell University (Ithaca, N.Y.) in 1984 and an M.S.E.E. from Northeastern University (Boston) in 1990. From 1984 until 1999, he worked at Raytheon Co. (Lexington, Mass.) on the materials characterization, growth and processing of III-V compound semiconductor devices. He has been with M/A-COM since 1999, and currently is the engineer responsible for backside GaAs wafer processing.
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