Deposition and Etch Blast through CD and Materials Obstacles
Alexander E. Braun, Senior Editor -- Semiconductor International, 12/1/2000
 |
At a Glance | | |
|
| ||
| |||
"The problem facing deposition is getting to thinner gate oxides for CMOS," said Willem Vermuelen, director of central marketing for ASM International (Bilthoven, Netherlands). "They're as thin as 20 to 15 Å, and it's easy to tunnel through the oxide and damage electrical integrity — we stretch this through wet oxidation. Within two years we must go to new high-k materials."
"There's a significant challenge in dielectric etch," said Gerald Yin, vice president and general manager of Applied Materials' Etch Products Business Group (Santa Clara, Calif.), "with the front end, high-aspect ratios (HARs) and self-aligned logic contacts, which fall within critical dielectric etch. We're dealing with shrinks from 0.20 to 0.10 µm and HARs from 10:1 to 15:1 or higher, on contacts with multilayer stopping depth. We're confronting self-aligned contacts with different structures, shallow or deeper, and the requirement to stop on the nitride shoulders with a small bottom opening of 0.05 µm or smaller. Meanwhile, sealed contacts must be opened without an etch stop."
| 1. Deposition and etch technologies are developing to cope with demanding requirements imposed by larger wafers, shrinking features, higher aspect ratios, and exotic materials never before considered by device manufacturers. Shown here is a high-volume copper ECD system. (Source: Semitool) |
The dielectrics turmoil
At Applied, state-of-the-art in deposition is high-density plasma for gap-fill applications. "Those include STI, pre-metal dielectrics, use of PSG with planarization, CMP process and intermetal dielectrics including last metal, which more recently has been a simple dual passivation layer of oxide and nitride," said Mark Beals, chief marketing officer for Applied's Dielectrics Systems and Modules Products Group.
"Plasma CVD use for dielectric films has boomed," he continued. "It's being used for 0.18 µm and beyond, particularly copper damascene. Plasma CVD films serve as anti-reflective coatings, barriers, caps and hard masks in addition to bulk IMD layers."
Another reason for the technology's proliferation is the demand for low-temperature processes. "There's a decline in thermal processes' use over 700°C," Beals said. "The need to work at lower temperatures while providing a stable film will become more critical." Cobalt silicide has been discussed, but apparently other silicide structures of the conductor gate structure material are not as sensitive. Applied expects CVD dielectrics to be used until the 0.10 µm node. Then it will be a question of what the preferred materials method is at 0.07 µm.
Atomic layer deposition
ASM is attempting to benchmark several thin-layer, high-k materials against the normal depletion method, and use atomic layer CVD (ALC). "We're working with aluminum oxide, which has possibilities," Vermuelen said. "Work remains to be done to find a gate material solution." DRAM applications demand a thinner nitride, and this has been obtained with HSG. "Eventually, something else will be needed. Tantalum oxide was a candidate, but exhibits high current leakage. For capacitors, we're working on a solution using single-wafer ALC."
ALC can deposit exotic materials, and multiple layers of materials in any sequence on top of each other. "Five years ago, ALC wasn't suitable because it takes one or two minutes per layer, and as many as a thousand layers might be needed — that was too much time," Vermuelen said. "Today, we're looking at four layers, making ALC technology feasible. With it, we can tackle high-k for capacitors, gate oxide."
Using ALC, ASM and Philips have produced possibly the thinnest gate dielectric with commercially acceptable leakage current, demonstrating an electrically insulating layer stack with a thickness of four to five SiO atoms. This 0.011 µm effective thickness ultra-thin layer's insulating characteristics are almost a million times better than silicon's.
To produce it, SiO was abandoned for a layer composed of zirconium, aluminum and oxygen. These thin electrically insulating stacks will be necessary for 0.07 µm devices.
Seed layer and copper reliability
The number of interconnects required for increasingly smaller devices are a gating factor, contends Jurek Koziol, vice president and general manager of Electrochemical Technology at Semitool (Kalispell, Mont.). "As they multiply in numbers and shrink in size, these leads must go to local transistors — there lies the major hurdle." Linewidth affects resistivity, and length and capacitance are other aspects — hence copper. The present predicament is the manufacturing steps required to make copper lines reliable, simple to produce, and of the correct (smaller) size. Also, barrier layers are needed to prevent copper from diffusing into the silicon.
"The difficulty with smaller linewidths is that, to fill the copper into the dielectric, it's necessary to provide the conduction layer," Koziol said. "This means a seed layer on the barrier, to allow the conduction of electrons and provide the electrochemical reaction site." This is done by patterning the dielectric, covering it with barrier and seed layers and plating copper into trenches and vias.
As vias and trenches become narrower and deeper, laying a continuous seed layer into the corners deep in these trenches is difficult because the current method — sputtering copper ions directly on the surface — is a line-of-sight technique that works well on anything presented full face to it, but oblique angles allow few atoms per square centimeter of surface coverage. A solution is to improve sputtering, using something akin to CVD to provide a conformal layer. A disadvantage is the CVD layer's inferior adhesion to the underlying barrier. Sputtering blasts copper atoms into a target — the barrier — which dig themselves into it.
There are electrochemical techniques to strengthen deposited layers where the thin adhesion layer of sputtered seed is insufficient for normal electroplating. "A side issue is that when you deposit a thin copper layer and transport the wafer the layer oxidizes," Koziol said. "Normally, the oxide is etched away by the electrolytic solution, but we use a chemistry to reduce the oxide layer to copper, avoiding a net removal of the copper layer from the plating surface."
This process allows the depositing and strengthening of the seed layer. It is a conformal plating technique that produces sufficient seed-layer build-up for the next plating step. "By knowing the thickness profile on the wafer's macroscale, we can adjust plating recipes to compensate for what would otherwise be deleterious non-uniformity in trenches and vias," Koziol said.
This is combined with a metrology station capable of measuring incoming seed-layer thickness in multiple spots. This provides a thickness map for the plating chamber used to correct the seed's non-uniformities — whether done with ECD seed or electrolytic fill process — with a plating recipe derived on the spot.
Etch and the environment
Etch processes are using more environmentally acceptable materials. According to Jim Clark, applications specialist at BOC Edwards (San Jose, Calif.), for example, NF3 is a gas that contains no chlorine.
"Some etch gases did have chlorine," he said, "but weren't CFCs. Specifically, gases such as boron trichloride, BCl3, or sometimes even chlorine itself, Cl2, were used. But again, no CFCs, with their ozone-depleting potential."
Any of these have pluses and minuses. An issue today with PFCs such as CF4 and C2F6 is that they are greenhouse gases. Although they don't damage the ozone layer, they may contribute to global warming. Widely used gases, each with its own problem, also include Cl2, HBR, C3F8.
The problems with new gases such as NF3 are supply, not environmental ones. Although NF3 is corrosive, it can be easily abated in the fab. "It's nice to have a molecule that readily falls apart," Clark said. "That was the problem with CF4 and C2F6— the molecules were too stable and made their way into the upper atmosphere."
Even so, NF3 abatement is not trivial. "Whenever you break something down and hydrogen fluoride results, there are corrosion and health issues," Clark pointed out. "However, it's something you can tackle, whereas the PFC global warming issue is tougher because those molecules are stable and harder to abate. You can break them down in abatement equipment, but it takes a higher energy input. It is all a matter of trade-offs."
The etch landscape
"Etch is long-lived," Beals said. "With copper, the overall stack thickness is reduced. That was critical because etch faced ever-increasing HARs." HAR etch is a hurdle: how to deal with a 20:1 HAR at 0.15 µm — physically getting a species in a deep narrow channel. "Copper interconnect relieved somewhat escalating aspect-ratio pressure," he said. "This isn't to say that there aren't going to be aspect-ratio-sensitive applications, such as contact etch. But via etch and the rest have a long life. CVD oxides, FSGs are established and I see that as a good 0.13 µm candidate. The Black Diamond product is emerging, and it'll find its place between 0.13 and 0.10 µm."
The back end's etch challenge is focused on dual-damascene, with CVD and thin-film companies wrestling with spin-on or CVD materials, while integration work struggles with process sequencing. "A preferred solution," Yin said, "is a via etch followed by the trench etch using a nitride stopping layer, or no stopping layer at all. Cost, complexity and k-value considerations make it preferable to avoid a stopping layer, but this limits the process window and integration and does not provide a robust performance. This is why engineers add additional BARC or photoresist to protect corners, minimize microloading and improve bottom stopping layer loss. Neither materials nor process integration are finalized."
Device yield improvement and defect reduction are important, as are downtime and throughput. Like others, Applied is working on wafer performance improvement, process technology, and production environment whole-system performance. "Everyone's focused on tool technology for dielectric etch," Yin said. "A dominant dielectric etch technology is RIE-based, with a medium-density solution and a large process window."
RIE technology has run in deposition mode. The fab runs wafers through the chamber, depositing fluorocarbon polymers until they begin flaking, signaling that the chamber needs cleaning. "This has worked well," Yin said, "but the number of wafers per chamber clean is unpredictable and constrained, with a distribution between a few hundred wafers to more than 5000." Another restriction is limited process tunability, because the chamber has only one rf power input with a biased RIE mode.
Decoupled plasma source technology is an RIE alternative. It has two rf power inputs, one from the bottom through the cathode, another from the top. These sources offer additional tunability because there is a top power input that, in addition to bias power, can change process behavior. "For every wafer that's ashed, it's possible to run the top source in a short cleaning step, so the chamber's always clean," Yin said. "We can run from 10,000 to 20,000 wafers." Another advantage is process integration flexibility. Particularly with dual-damascene, it is possible to etch the via or trench the main etch and physically remove photoresist, then nitride. Up to five steps can be implemented in one chamber.
However, dielectric etch technology has hurdles. Most problems with top plasma source are related to its high efficiency in dissociating neutral species. The dissociation is too high and ion densities are higher than desired. Plasma sources without dissociation control exhibit less selectivity to photoresist and a narrower process window between selectivity and etch stop.
Etch and new materials
A system that etches entire structures is an ideal solution. It must open the hard mask in situ, etch the low-k, strip the resist, then etch the barrier layer. These films can have oxides, nitrides and low-k dielectrics with resist and they must be etched with appropriate selectivities and etch rates.
Lam believes dual-frequency confined technology is an answer. "It has the flexibility," Seto said. "Many of these processes have been required in oxide damascene, especially resist strip and barrier open. Systems proven with oxide damascene in volume production have the advantage of the experience on how to integrate with copper and the in situ processes without device damage.
All that remains is optimizing for the particular low-k, whether organic, inorganic or porous." (Fig. 2)
An advantage of such a system is its pressure range, which permits high-pressure resist strips and medium-pressure barrier opens along with low-k etch. "The challenge with low-k etch is similar to the balancing required for HAR contact etch in DRAMs. With HAR contact etch, it is difficult to maintain the selectivity needed without the process drifting to the point of etch stop," said Seto, adding that this is a similar issue with low-k. "Device makers tried high-density then moved to medium-density because of their wider process window. For low-k etching, the wider process range enables high-selectivity etch without etch stop. For defectivity issues we must ensure that the processes and chamber materials don't interact when oxide, low-k and nitride etches, and resist strip are done in the same chamber." Seto added that, with confined plasma, only a small portion of the chamber is exposed. "We can control these surfaces through material optimization and waferless autocleans."
CD control and 300 mm
"Oxide processes will be a major hurdle in moving to lower dielectric constants," said Steve Crapps, senior manager for Strategic Technologies at Hitachi America (Carrollton, Texas). "Specifically, finding materials with desired dielectric properties and no bleed-through issues with other materials, which can be etched with the CD and depth control tolerances smaller features require."
"In memory, they're still working with metal etch, and metal challenges lie in the thinner resist required to meet lithography requirements. The necessary selectivity to etch desired metal thickness with the available resist on top of the features makes this difficult," Crapps said. "The two key issues are larger wafers, which make CD and process control processes across the surface more challenging, and finding dielectrics that can be etched while maintaining the same profile and CD control level."
Particles remain critical: "Although defect control has always been a major concern, it's more so now," Crapps said. "We have customers whose expectation is <10 0.09 mm particles across an entire 300 mm wafer through the whole wet clean cycle. Incredibly, it isn't excessive. Logic devices, for example, lack redundancy — one particle may equal one dead die. Even without metal etch since the implementation of damascene there are still multiple etch levels, which can result in a lost die per particle generated by an individual etch step."
It is not just the gate that is changing, but also the gate oxide. Engineers are leaving SiO2 for other materials. "We have customers bringing up titanium and other materials as gates, trying to stop on an oxide on a titanium etch with oxide thicknesses in the 20 to 30 Å range. The industry must settle on one or two high-k materials," Crapps said. "We've etched SiLK, Black Diamond and others, all of which have drawbacks."
Over this same period, metal gates will also be a challenge. "How metal gate plays out in terms of materials will be another source of headaches," Crapps said.
A significant problem is CD control on increasingly smaller features, across 300 mm worth of wafer. Normally, 5% to 7% CD control is required. Thus, with a 0.10 µm line, there is only a 0.005 to 0.007 µm CD s across the wafer, or 50 to 70 Å on a 300 mm wafer. With the shift from 0.10 to 0.07 µm, this will drop to 35 Å of s. Maintaining CD control will be tough because, just like particle defect density, the target keeps shrinking. The chamber will have to be extremely stable, and that stability requirement must be integrated to the particle control requirement.
Dry etch of metal interconnects may disappear. It will be a while before this happens — especially with oxides and dielectrics — but by going to dual-damascene metal etch is eliminated although oxide etch remains. Perhaps damascene gates, a concept currently under evaluation, will become common, but problems such as ion implant, gate/oxide/junction interactions must be solved.
Films and materials
Tim McEntee, general manager for PECVD products at Mattson Technology (Fremont, Calif.), believes logic devices drive deposition technology. "Much of the technology will be impelled by dual-damascene back-end requirements," he said. "As materials change, integration issues arise. Presently, thin nitride and other materials are being developed for etch stop layers, and work is underway on low-k." McEntee added that device makers are migrating to FSG as an initial move into dual-damascene, or using basic oxide.
Both spin-on and deposition-type materials are under consideration. "We have silicon oxycarbide films that we're working on for low-k; others are working on different materials, each with its own integration problems," McEntee said. "Much of the work will involve how to deposit the films and the interface between the layers required to build reliable devices."
Issues with spin-on materials deal with thermal sensitivity because they are organic polymers. "This means outgassing," McEntee said, "because they must be cured at some temperature, but the device must be processed after laying down those layers. How well they hold up through the thermal processing taking place between each layer dictates how they integrate." Silicon oxycarbide films bring other concerns.
New materials and integration
| 3. Left, an iridium upper electrode with >85° profile used for high-k dielectric capacitor. Right, a vertical profile of ruthenium, etched with an oxide hard mask. Aspect ratio is ~4:1 at a 0.3 µm pitch. (Source: Tegal) |
Integration is difficult and high- and low-k dielectrics bring unforeseen problems. High-k dielectrics are complicated compounds with things like titanates, which before nobody considered for semiconductor use. That oxide is less stable than SiO2 and undergoes phase changes across temperature cycles, creating thermal budget complications. It also bleeds oxygen from its lattice structure, which then permeates through electrode materials.
Materials' complexity is turning device makers to suppliers for expertise. "A customer is investigating MRAM technology, which incorporates magnetic materials into a CMOS-like process," DeOrnellas said. "They're asking us which materials to use for its process integration to avoid affecting the film's magnetic properties."
MRAM's application is non-volatile memory. "Non-volatile etching byproducts come with non-volatile memories," DeOrnellas said. "When etching materials like platinum and others you come to grips with the fact that even at low pressures (the 1 mTorr range) using normal chemistries and normal temperatures, they aren't volatile. You must manage the etch without turning into an ion mill, which has fundamental linewidth limitations."
Ion milling characteristics must be balanced with those of etching. Tegal uses multiple frequencies to alter plasma conditions, producing the amount of ion energy or ion milling etch characteristic needed. "We must accurately monitor the wafer's surface for etching conditions, position, temperature, etc. We've spent considerable time and resources developing sensor capabilities to manage the wafer's surface beyond just a nuts-and-bolts process of generating a plasma of x density."
Metrology and feedback loops are getting complex. For MRAM, for example, device makers are attempting to etch a structure with 10 layers of material within a 300 Å span. "On the deposition side, you're managing seven to 15 monolayers of material, but when we etch it we must look at each interface in 10 to 50 Å increments," DeOrnellas said.
At 0.10 µm feature sizes with new materials to deposit and etch, while managing integration, suppliers face large-magnitude challenges. Never, as an industry, have we considered such a broad spectrum of materials for integration. Manufacturers are talking about elements in the Periodic Chart that most people do not know exist such as hafnium and niobium — exotic rare-earth materials that five years ago nobody would have considered putting into a device.•
