Samsung Fabricates 70 nm Devices with Traditional Materials

Seungheon Song, an invited speaker from Samsung Electronics (Kyunggi-Do, Korea), will present guidelines and proposals aimed at addressing CMOS transistor scaling issues beyond 100 nm at this month's IEEE IEDM in San Francisco. Among other recommendations, Song and colleagues will propose the use of selective epitaxial growth (SEG) as a viable technology for producing 1.3-1.7 nm thick oxide-equivalent gate dielectrics.

SEG technology may prove to be especially important, according to the engineers, because it can help lessen variation in gate length at a smaller L_gate, thereby reducing the potential shift in threshold voltage (V_th). Samsung fabricated high-performance CMOS transistors with 70 nm polysilicon gates with 1.4 nm oxides. The transistors showed excellent current drives of 860 µA/µm (NMOS) and 350 µA/µm (PMOS) at I_off of 10 nA/µm and V_dd of 1.2 V. This implies that ultrathin gate oxynitrides with poly gates may extend to the 100 nm device generation, delaying the need for high-k gate dielectrics and metal gates.

For every difficulty encountered with CMOS scaling (Table), a number of changes in process conditions, physical structures and materials have been proposed across the industry. Samsung engineers emphasize, however, that new approaches such as high-k dielectrics, metal gates and laser annealing do not currently meet manufacturing requirements, especially with respect to process integration.

Samsung designed experiments to test the value of employing super-steep retrograde channel profiles using SEG and to determine the limit of oxynitride dielectric scaling. The process flow formed the shallow trench isolation region, followed by well and channel ion implants. Then undoped silicon was grown using SEG by LPCVD. Either RTP or furnace processing could be used to form a stacked structure of oxynitride with LPCVD nitride. To reduce poly depletion, additional ion implantation steps were performed before gate patterning. The engineers used KrF lithography with size reduction and an SiON hard mask etching technique to control gate-length uniformity. Next they performed a reoxidation. To reduce short channel effects, they performed high-dose low-energy (<3 keV) source/drain (S/D) extension implants and HALO implants. Then came the RTP activation step and nickel silicidation.

By analyzing the transistor characteristics with 1.7 and 1.3 nm oxides, and with and without super-steep retrograde channel profiles, Samsung found the thinner gate dielectric suppressed V_th roll-off and an SSR channel further reduced V_th roll-off for both the NMOS and PMOS devices. This suggests that the SEG helps scaling by reducing the V_th variation due to L_gate variation for the same L_gate. For SSR devices, both I_on and I_off reduced at the same V_th due to reduced sub-surface punch-through and increased body effect, respectively. The SSR's lower channel doping density increases carrier mobility and transconductance.

Using a gate leakage current limit of 1 A/cm², C-V behavior indicates an oxide-equivalent thickness limit of 1.4-1.5 nm. By studying the drain current and gate leakage versus gate voltage behavior for NMOS/PMOS transistors of various L_gate and oxide thickness of 1.3-1.6 nm together with gate leakage modeling, the engineers determined that for thinner gate oxides drain current degrades subthreshold characteristics and sets the limit of I_off for a given L_gate. They increased performance by properly optimizing the overlap length (between gate and S/D) while considering gate-to-S/D capacitance and S/D parasitic sheet resistance. The process that formed reliable 70 nm CMOS devices with1.4 nm gate oxides was also characterized by careful control of shallow-junction B or BF₂ dose and an RTP activation with minimal thermal budget. Samsung determined that gate oxides thinner than 1.4 nm can be used as device size (L_gate and overlap) scales further, without requiring high-k dielectrics. Reliability studies revealed good time-dependent dielectric breakdown and breakdown voltage distribution for oxides as thin as 1.3 nm.