Thin Chip Integration Provides Manufacturing Flexibility
John Baliga, Associate Editor -- Semiconductor International, 12/1/2000
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| John Baliga,Associate Editor |
Wafers containing the smaller top chips are bonded to silicon carrier substrates with a reversible adhesive. They are then thinned by grinding, followed by etching and finally chemical mechanical planarization (CMP). These bonded wafers can be diced using conventional dicing equipment, producing pieces that can be handled like conventional die.
A thin layer of adhesive is applied to the wafer containing the large base chips, and the top chips are attached using conventional die bonding. After the adhesive is cured, the carrier chips are removed and the excess die bonding adhesive is removed by plasma treatment.
Photosensitive BCB is added, making a planar surface. Vias to all the contacts are made lithographically, and the BCB is cured. The aluminum bond pads are cleaned by backsputtering in argon. A plating base consisting of a 200 nm Ti:W diffusion barrier and 300 nm copper seed layer is sputtered, and a photoresist plating mask is applied and patterned. After 5 µm of copper is plated, the mask and plating base are removed.
A second layer of photosensitive BCB is applied and patterned as the solder mask. Under bump metal deposition and bumping completes the process. Starting with the first BCB layer deposition, the entire process simply follows the standard wafer-level packaging process, except the thickness of the first BCB layer is determined by the top chips. Fraunhofer's TCI test vehicles exhibited the same level of reliability as its wafer-level packages.
Using this technique provides the equivalent of customizable chips, as well as an alternative to flip-chip-on-chip, stacked chip and other multichip techniques. The "customizable chip" capability allows the final decision on exactly what chip is used in the final product to be delayed to the last possible step.
In some cases, the demand for a class of similar chips may be known, but the exact breakdown within that class may not. Instead of making multiple single-chip products, each with unknown demand levels, the base chip can be made to match a known demand level. Putting the customizable portions on separate chips takes most of the inventory risk away from larger chips and puts them on the customizable portions, which are smaller and less expensive.
As product lifetimes decrease and product customization increases, more customization will be performed later in the manufacturing process. Packaging and assembly operations will be required to perform more customization, and techniques such as TCI will likely be a part of the solution. •
REFERENCESFor additional information on assembly and packaging go to www.semiconductor.net/assembly.
