IMEC Investigates High-k Gate Dielectrics For Deep Submicron Devices

Brian Dance, Contributing Editor

Researchers at IMEC (Leuven, Belgium) have shown that the reliability of conventional thin oxide dielectrics is worse than had been previously anticipated. They conclude that the introduction of alternative gate insulating materials will be unavoidable for process technologies scaled to <100 nm. Because the development of such a critical layer in an IC is possible only through a large-scale international collaboration, IMEC has set up an Industrial Affiliation Program, initially with its strategic partner ASMI, to develop gate dielectrics and gate electrodes for sub-100 nm devices. IMEC wants to develop a manufacturable process for dielectric films that are <1.5 nm thick.

The dielectric layer must have a low defect density and the ability to be reproducibly deposited with accurate thickness control. The material must have low leakage current and hysteresis and a high charge carrier mobility. It should demonstrate a 10-year lifetime under normal operating conditions with a 0.01% failure rate at elevated temperatures and a total gate area of 0.1 cm².

In October, IMEC and International SEMATECH entered into an agreement to collaborate on the development of manufacturable processes for the gate stacks required for use in sub-100 nm devices. IMEC will provide its expertise in reliability and device development related to high-k gate dielectrics in support of SEMATECH's overall program for sub-100 nm CMOS technology scaling.

IMEC and ASMI are investigating atomic layer chemical vapor deposition (ALCVD) to deposit the thin dielectric films, because it offers some unique advantages over competitive approaches. Researchers say that this technique results in perfect thickness and uniformity, as well as giving composition control over large substrates.

SEMATECH and IMEC will work together to develop effective materials and processes for gate stacks for the 100 nm technology node and also for smaller nodes. This work will include:

• The evaluation of high-k gate dielectric materials.
• The development of processes for depositing these materials by ALCVD and metalorganic CVD.
• The evaluation of various metal gate electrodes.
• The development of cluster tool integrated processes.
• The fabrication of etched gate structures.
• A feasibility study of the potential integration issues in full CMOS processing.
• Cleaning and contamination control.
• The physical and electrical characterization of the high-k materials.
• The reliability of gate stack and transistors.
• Metal gate electrodes.
• Environmental, safety and health considerations.

Initially, the collaboration will aim to achieve an effective gate oxide thickness of 1 nm, but the final aim is to demonstrate the feasibility of a 0.5 nm equivalent oxide thickness stack.

"Silicon dioxide, which has been the heart of the MOS transistor for over 40 years, now has to be replaced," said Marc Heynes, director of IMEC's high-k program. "This enormous technological challenge requires a global collaboration to meet the requirements of the International Technology Roadmap for Semiconductors." •