Integrated Dry Clean Without Surface Roughening

Maria A. Lester, Associate Editor -- Semiconductor International, 12/1/2000

Maria A. Lester, Associate Editor

The 1999 Roadmap states that gate dielectric thickness will be 1.0 to 1.5 nm, equivalent silicon dioxide thickness, at the 100 nm technology node. Although high dielectric constant materials such as tantalum oxide are emerging, thermal silicon dioxide or nitrided silicon oxide will still be commonly used at the 100 nm technology node. In fact, studies show that the quality of thin gate oxides is dependent on the silicon surface roughness immediately preceding the oxidation process.

One method to maintain the integrity of the Si/SiO₂ interface is to use a single-wafer cluster tool where the silicon surface is conditioned in a dry, vacuum chamber and transferred to a rapid thermal oxidation chamber. FSI International (Chaska, Minn.) researched such a surface conditioning process, using anhydrous HF for native oxide removal and photo-activated chlorine for organics and metals removal. The researchers recently presented the results at the Symposium on Ultra Clean Processing of Silicon Surfaces. This clustered single-wafer dry cleaning process is being used in the ORION Dry Cleaning Module, resulting in clean, smooth interfaces for film deposition. The module is designed for full two-sided processing, where both sides of the wafer can be cleaned at the same time. It is designed to be a final clean following wet, pre-diffusion cleaning, which removes the bulk of contaminants before the gate stack cluster. Recent studies at Lucent Bell Labs showed better performance of ultra-thin (10 Å) gate oxides grown on UV/Cl₂-treated silicon surfaces.

This dry cleaning technology has been in development for about 10 years and matured through a series of collaborations between FSI and leading universities, sponsored partially by a two-year grant from the NIST Advanced Technology Program. The photochemical UV/Cl₂ technology preps surfaces before critical depositions, such as pre-gate, selective epi and via liner, enabling 130 nm processing. In the chamber, Cl₂ gas flows across the wafer, which has a UV lamp housing above and below (for dual side). UV disassociates Cl₂ into Cl ions and activates surface chemistry, removing organics and trace metal contaminants. UV also heats the wafer. The UV/Cl₂ process is used in combination with an anhydrous HF oxide etch, where the wafer is held static and attains a uniform oxide etch. The ORION module performs integrated final surface preparation prior to film deposition, including organic removal, oxide etch and light metals removal, while maintaining particle neutrality and surface roughness at ~180 sec per wafer.

In the Lucent Bell Labs study, surface roughness was measured as a function of lamp power and exposure time during the second UV/chlorine step (Table). Controllable process parameters are exposure time and voltage (tunable 300 to 1500 W), which modulate the extent of Cl₂ disassociation and on-wafer temperature. Temperature at the beginning of the UV/chlorine step was also varied. It was allowed to rise during the UV exposure, depending on the power level and exposure time. Results showed that at high UV power and extended exposure times, pitting and roughening occurred. At low UV power they found that exposure time could be as long as 45 sec without roughening the silicon surface. Further TXRF analysis indicated there was no metal contamination(<10¹⁰ atoms/cm²) during the cleaning sequence.

Table. Surface Roughness Measured by AFM as a Function of UV/Cl2 Treatment
Process tests during UV/Cl2 step		Wafer temperature (°C)		RMS roughness (Å)
No.	Test conditions	Start	End	Pre	Post	Comments
1	Pretreat/oxide etch/reoxidation			0.77	0.66
2	Pretreat/oxide etch/UVCl2-hi power-50 sec/reox	40	>300	0.65	1.76	pits
3	Pretreat/oxide etch/UVCl2-hi power-10 sec/reox	40	~100	0.63	1.76	pits
4	Pretreat/oxide etch/UVCl2-hi power-1 sec/reox	~100	~100	0.70	0.92	start of pits
5	Pretreat/oxide etch/UVCl2-lo power-90 sec/reox	~100	~150	0.81	3.75	pits
6	Pretreat/oxide etch/UVCl2-lo power-45 sec/reox	~100	~125	0.67	0.68
7	Pretreat/oxide etch/UVCl2-lo power-1 sec/reox	~100	~100	0.75	0.72
Pretreat = short UV/Cl2 step to remove organics and stabilize wafer temperature at 40°C; Oxide etch = anhydrous HF oxide etching; Reox = UV/O2 silicon reoxidation (Source: FSI)

Control of the UV lamp power and exposure time allows the dry cleaning process to prepare the silicon surface for gate oxidation without roughening. FSI's clustered dry clean process removes native oxide, trace organic and metallic contamination without affecting the substrate, following traditional wet cleaning. •

For additional information on clean processing go to www.semiconductor.net/clean.

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

• Topics
• Author

Related Content

 

By This Author

• Single Wafer Ozone Clean Done Without Megasonics
• Selective Material Removal for Nanostructure Formation
• SEMICON West Adds New Programs
• Membrane Purifies Wet Etch and Clean Processes
• 2003 Top Fabs
• » MORE

SPONSORED LINKS