Test Structures for a faster SOC Yield Ramp

SOC product yield analysis is complicated by the need to differentiate between systematic forms of yield loss (from processes and chip design), parametric yield loss (because of circuit issues) and random yield loss (from random defects). The module process test chip uses structures to verify design rules (pattern density, overlay, depth dependency, etc.) and device characteristics (resistances, etc.), as well as the random defect size distribution (using a NEST structure). The NEST approach allows users to extrapolate defect distribution parameters D₀ and p from the measured defect data using an optimum fitting equation.

The SRAM chip portion of the LSI test chip is designed with various kinds of structures (GC-CS short, GC short, VSS source/CS open, AA short, etc.) to predict failure modes without having to perform physical analysis using a SEM or other tool. For example, models for an open in a stacked contact at via 3 and a short at metal 4 can be matched to particular failure modes using an SRAM failure bit map. In this way, Toshiba engineers can quantitatively evaluate and perform LSI process-level integration with a short turnaround time.

The engineers resolve the SRAM's random from systematic defect density using:

D_0SRAM = D_S+D_R

In these equations, A_c is the critical area, AA is the transistor active area and M4 is the metal-4 layer. By simultaneously reducing each failure mode, test chip yield is rapidly improved. Because the engineers first reduced random yield using the module test chip, most of the SRAM test chip failures detected were systematic in nature.

Next, parametric failures were identified, also using the SRAM test chip. The difference between the defect density trend of the SRAM and the defect density trend of each of the SOC products gives the parametric defect density of the product. Once the parametric failures are addressed through mask refinement and other means, the product yield should match the SRAM yield trend.

Thus, quantitative analysis using a suitably designed LSI test chip with an SRAM test component, together with a module process test chip, can be used to differentiate between random, systematic and parametric failures. This methodology allowed both lower initial defect density of Toshiba's 0.18 µm products with respect to its 0.35 µm generation as well as fast yield ramping of critical SOC devices.