Two Alternatives to Cu CMP Now Available

Peter Singer, Editor-in-Chief -- Semiconductor International, 12/1/2000

Peter Singer, Editor-in-Chief

Two different companies have developed interesting alternatives to copper chemical mechanical planarization (CMP). Alternatives to Cu CMP are sought because it's often difficult to control erosion and dishing during CMP, and because it's uncertain if Cu CMP will be compatible with low-k dielectrics, many of which have low mechanical strength and can shear during CMP.

One company, ACM Research (Fremont, Calif.), recently introduced a process called SFP (stress-free polishing), in which copper is removed by essentially reversing the electroplating process. Another company, SEZ (Phoenix), is working to further develop a spin-etching planarization, which is a wet-removal process using no physical contact with the wafer surface.

ACM's SFP

ACM is actually introducing two new processes, one for Cu electroplating and the other, based on a similar equipment platform, for SFP. The company's electroplating process is unique in that it can work with a very thin seed layer, which president and CEO David H. Wang believes will extend the Cu electroplating process from 0.13 to 0.035 µm. This type of continued scaling is dependent on thinner and thinner seed layers. The thinner the seed layer, however, the harder it is to get a uniform current from the edge to the center of the wafer; 300 mm wafers only compound the problem. Wang said that existing techniques run into problems with thin seed layers where the center plates thinly or not at all. ACM's approach avoids this problem by plating "donuts" of copper from the edge of the wafer inward. The company has achieved a thickness variation of 1% (1  s) with a 50 Å seed layer, and can use seed layers anywhere from 500 to 50 Å.

1. The uniformity achieved in ACM's stress-free polishing process. (Source: ACM Research)

In ACM's SFP technique, a similar chamber is used (i.e., wafers are immersed in a copper plating solution) but the current is reversed so the copper is removed from the wafer surface. A "partial polishing" technique is used, similar to the way the plating is done. "We can change the potential drop across the wafer so that polishing occurs only in the center area or edge area," Wang said. Also, multiple polishes can be used to improve uniformity (Fig. 1). The main advantage of the approach is that, in addition to removing stress on the wafer, it eliminates slurries, pads and abrasion, as well as process-induced scratches and surface defects. The company reports that it can achieve a CoO of less than $2 per wafer, about 60% less than with conventional CMP.

SEZ's SEP

SEZ, headquartered in Villach, Austria, with a U.S. office in Phoenix, has been working on another alternative to Cu CMP in conjunction with Honeywell Electronic Materials (see "Copper CMP: A Question of Tradeoffs," Semiconductor International, May 2000).

2. SEZ's SEP process also shows good uniformity and fast copper etch rates. (Source: SEZ)

The process is based on SEZ's spin etch process (SEP). During SEP, the wafer is suspended horizontally on a nitrogen cushion above a rotating chuck. The substrate is held in place laterally with locking pins on the wafer edge. As the chuck and wafer are spun, wet etch chemistries are dispensed onto the wafer. A planar final surface is achieved by using an appropriate etching solution and spinning the wafer while removing the excess copper. De-ionized water and nitrogen are then applied onto the wafer to achieve rapid cleaning and dry-in/dry-out processing. Research results to date have demonstrated selective copper removal at 14,000 Å/min with 3% (1 s) non-uniformity and planarization of features up to 2.5 µm in width with no dielectric erosion. Figure 2 shows the fast copper etch rates and low non-uniformity achieved with the SEP process. •

For additional information on wafer processing, go to www.semiconductor.net/wafer.

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