Strained Silicon Seizes the Day

Strained silicon is a viable technology; it is in manufacturing today and is an enabling technology for the 90 and 65 nm nodes. These were some of the conclusions from Semiconductor International's latest technology webcast, "What's Happening in Strained Silicon ?" (see www.semiconductor.net/webcasts to view the archive). At this event, Serge Biesemans of IMEC (Leuven, Belgium), Ken Uchida of Toshiba (Yokohama, Japan) and Rama Divakaruni of IBM (Hopewell Junction, N.Y.) presented different approaches to creating strain in the silicon channel (Fig. 1 ), performance gains, some of the limitations of strain, and the differences between local and global strain for both bulk silicon and ultrathin-body devices.

1. Maximum mobility enhancement associated with the various types of stress engineering methods including SiGe stress relaxed buffer layer, S/D engineering and stress liner. (Source: IMEC)

Biesemans, director of the CMOS device technology group at IMEC, said that one of the reasons strain engineering is so important is because it not only increases mobility of charge carriers in the channel, it also reduces the S/D series resistance. "There are two ways of thinking about it. The germanium allows a higher activation, and that by itself usually reduces series resistance. The second reason refers to what's happening in the channel. In that slab of silicon between the source and drain the mobility is increased, so this reduces the series resistance."

Strained silicon has also saved the day when it comes to Moore's Law. The lack of a manufacturable high-k gate dielectric has forced manufacturers to stick with an oxynitride, and without the ability to scale the thickness of this oxide further, there was a need for a new scaling parameter, according to Biesemans, to get low series resistance and continue to drive I_dsat. Strained silicon provided this performance.

At IBM, Divakaruni, senior technical staff member of the systems and technology group, showed that a change from unstressed films to a dual stressed liner allowed a 15% increase in effective drive current in the NFET device and a 32% increase in the PFET devices. "We have fabricated the dual stressed liner in both single and multicore processors, giving a yield equivalent to the 90 nm flow." Divakaruni added that they have achieved a 24% improvement in transistor performance over conventional 90 nm CMOS processing (Fig. 2 ), and the technology is easily extendible to the 65 and 45 nm nodes. "At the 45 nm node, the dual stressed liner will definitely be used. The question is whether it will be sufficient to get the performance needed at the 45 nm node," Divakaruni said.

2. The tensile (top) and compressive (bottom) stressed nitride liners were successively deposited and etched after silicide formation and before ILD deposition/contact formation. (Source: IBM)

Global strain, generally implemented across the entire wafer as a SiGe relaxed buffer layer ~3-4 µm thick with a strained silicon layer grown over it, can achieve up to 80% mobility enhancement with a germanium concentration of 20%. Unfortunately, for sub-100 nm devices, global strain loses its mobility enhancement and I_dsat scales down with gate length, leading to only 10% benefit.

Uchida conducted experiments with a wafer bending apparatus to compare uniaxial and biaxial stress effects in bulk silicon and ultrathin-body MOSFET devices. Uniaxial stress was applied along the carrier transport direction in both <100> and <110> devices using a (001) wafer, 10 nm oxide and 200 × 100 µm devices. Electron mobility was measured as a function of electric field. The experiments determined that electron mobility was most enhanced in the biaxial stressed wafers, followed by the <100> direction and then the <110> direction. However, Uchida noted, at higher electric fields, the difference was almost negligible. In the case of hole mobility, biaxial strain actually reduces mobility, while the better increase is associated with the <110> direction; there was some small gain in the <100> direction. All mobility results qualitatively agreed with piezoresistive coefficient calculations.

Interestingly, uniaxial stress had a significant effect on UTB MOSFETs, even with TSOI of 7 and 3.5 nm. In fact, the enhancement ratio in the 7 nm device was almost equivalent to that of bulk FETs, and in the case of the 3.5 nm device, subband structure engineering cooperates with strain engineering to further enhance mobility.