The Future of Silicon and Beyond
Ahmed A. Busnaina -- Semiconductor International, 5/1/2005

The future of CMOS has been generating great interest in the industry and academia. CMOS is expected to last for the next 15 years. Most would think that this is because of the scaling down of the fabrication process. However, the problem is much more than just scaling. The ultimate CMOS theoretical limit to scaling beyond the ITRS at room temperature has been shown to be 1.5 nm characteristic dimension, 0.017 eV switching energy, and 0.04 psec switching speed.1 The total power density at that limit for 1% duty cycle and 1% active transistors is 370 W/cm2.1 This illustrates that, if the thermal dissipation problem is not solved, we may have to give up the speed and density that come with nanoelectronics-based transistors. That leads to a path that does not involve conventional transistors. The industry is looking for new switch technologies that are energy-efficient and high-performance, with gain, scalability and reliability at room temperature.1 These switches would have to be no-charge-based and possibly a non-equilibrium system. The preferred non-charge switches would have to be those compatible with CMOS.
There are many challenges facing the industry in its path along the ITRS and beyond. The first challenge is near-term (2012-2020), which focuses on extending charge-based switch technology integrable with CMOS beyond the current CMOS scaling. The second is long-term (beyond 2020) and focuses on developing a new switch technology or a new "logic element" that can extend nanoelectronics beyond that of the conventional charge-based technology.
There are many new switch technologies: spin logic, phase logic, molecular devices, crossbar devices, cross-net devices, mechanical, biological or molecular switches, etc. Manufacturing of these switches would require very diverse fabrication and assembly techniques that may involve top-down, bottom-up or both. Fabrication of nano building blocks and nanostructures with uniform properties and size is essential for the assembly of nano devices. These nano building blocks need to be assembled with precise orientation and location over a large area in a short time. Research is also needed to develop nanoscale materials by design, self-assembly for functionality; nanoscale materials characterization and metrology; and nanoscale registration and alignment.
New research directions need to be addressed to augment current research efforts going on in the industry, universities and government research centers and laboratories. The first research area that should be addressed is heterogeneous process integration, such as the combination of hierarchical-directed assembly techniques with other processing techniques. The second is nanoscale metrology tools, such as in-line or in situ monitoring and feedback. The third is a high-throughput directed assembly. The fourth is nanoscale components and interconnect reliability. The fifth is nanoscale defect mitigation and removal and defect-tolerant materials, structures and processes (e.g., self-healing). The sixth is probabilistic design for manufacturing that addresses variability and noise at the atomic scale.2 A great deal of novel science is needed to enable high-rate/high-volume nanomanufacturing. One approach is the use of templates with nanoscale features that could enable 2-D and 3-D assembly of nano elements and their transfer to other substrates in a predetermined pattern. This would also require nanoscale self-registration and alignment that could be accomplished by chemical forces, which could bring matching features together and complete the physical registration.
These are very challenging tasks that could only be addressed if the industry, academia and government work together. The industry has focus centers that are geared toward addressing the near-term challenges. The National Science Foundation's Nanoscale Science and Engineering Centers, although not all focused on electronics, are addressing the long-term challenges. The industry is solidly involved in the near-term research, but has just started assessing the ongoing long-term research taking place at academia and government laboratories.
| Author Information |
| Ahmed A. Busnaina, William Lincoln Smith Professor and Director, NSF Nanoscale Science and Engineering Center (NSEC) for High-Rate Nanomanufacturing and the NSF Center for Nano and Microcontamination Control, Boston, www.nano.neu.edu |
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