Epitaxy Challenges for Strained Silicon in SOI Integration

The straining of a silicon crystal is a well-known technique to increase charge carriers' mobility, enhancing device performance. Since the introduction of strain in silicon has less dramatic consequences on a CMOS device's manufacturing processes than the switch to a new class of high-mobility semiconductors like germanium or III-V compounds, this more conservative approach is preferred. To be most effective, the strain in a silicon channel should be compressive for the hole conduction of the PMOS transistors and tensile for the electron conduction of the NMOS transistors. Since unstrained silicon hole mobility is on average three times lower than that of the electrons, prime focus has been given to the improvement of the PMOS transistor mobility. When the mobility ratio between PMOS and NMOS must be preserved for design reasons, NMOS mobility has to be improved concurrently. A solution that can tune NMOS and PMOS independently is therefore highly desirable.

Today, two approaches are widely used to obtain the desired silicon strain. One is based on developing the strain at the substrate level before the transistor is built. This is called the "global" approach. The other is based on inducing strain by means of "local" films at the transistor's periphery. Both approaches can be based on complex and challenging epitaxial technologies. Apart from introducing global or local strain in a very controlled way, epitaxy also offers the possibility to construct alternative device architectures such as silicon-on-nothing (SON), multi-gate transistors or finFET devices. Hence, epitaxial technology is now widely adopted as a critical tool to meet the device performance roadmap.

Tensile strain in silicon has been introduced by growing a pseudo-morphic silicon layer on a substrate with a larger lattice constant. A commonly adopted way to manufacture such "virtual" substrates has been extensively described by Fitzgerald et al., and consists in growing a strain-relaxed SiGe epitaxial layer on the wafer.^1,2 Under the right conditions, the degree of relaxation can be close to 100%. However, the SiGe relaxation process generates threading dislocations in the density, which must be carefully controlled and minimized. A state-of-the-art epitaxy process may include first a graded SiGe layer — a so-called "buffer" layer with adequately profiled germanium concentration — followed by a low dislocation density, strain-relaxed SiGe layer of a constant germanium concentration. The buffer layer's germanium profile is particularly critical, as it controls the relaxation and the generation and confinement of the threading dislocations that develop from the misfit dislocations at the silicon-SiGe interface. When the final germanium concentration is around 20%, the buffer layer thickness needed to meet crystal quality requirements is typically 2-3 µm. Depending on the epitaxy process' details, dislocation densities can be as high as 10⁶/cm² or as low as 10³/cm².

Subsequent growth of a thin silicon layer on such a strain-relaxed SiGe substrate leads to ~1 GPa tensile strain in the silicon, which improves electron mobility by ~50%. To obtain a maximum strain in the top silicon layer, its thickness should not exceed the "critical" thickness — the thickness at which relaxation sets in. This considerably limits the epitaxy process' thermal cycle, as the critical thickness is a strong function of the growth temperature. Typical values are ≤20 nm for the silicon layer thickness when grown on a 20% SiGe relaxed layer at an 800°C corresponding growth temperature.

Of particular importance to achieve high-quality and reproducible epitaxy of strained silicon is the fact that the growth takes place on a SiGe surface. The germanium in the SiGe is easily oxidized and much more volatile at high temperatures than silicon. Therefore, special precautions must be taken in the reactor hardware to control the native oxide's thickness on the SiGe surface, as well as its removal prior to epitaxy, to ensure the growth of a defect-free strained silicon layer.

All of the mentioned technologies are of a "global" nature; that is, all layers are grown over the entire wafer. As mentioned, the use of a strain-relaxed SiGe substrate leads to a tensile stress in silicon that makes the gap between NMOS and PMOS mobility even larger. Considerable effort was therefore devoted to develop a suitable solution for PMOS devices as well. One option is to increase the germanium concentration above 35%, at which value the tensile stress also enhances hole mobility. However, not much progress has been reported in terms of acceptable surface morphology and dislocation density of such layers.

Germanium's presence in the SiGe substrate is also a concern since it causes serious integration problems, such as thermally induced germanium out-diffusion into the strained silicon layer, which can decrease its strain. When germanium reaches the gate-oxide interface, a significant increase of interface trap densities can occur, degrading transistor performance and reliability. Dopant diffusion in SiGe is substantially different than in silicon, necessitating significant re-engineering of source/drain extensions.³ SiGe's lower bandgap also increases diode leakages and transistor off currents. This can noticeably amplify standby currents of circuits. Threading dislocations increase diode leakage as well; a threading dislocation density as low as 10⁴/cm² is required to minimize diode leakage impact.⁴ These integration issues, combined with equipment cross-contamination — concerns that emerged during the manufacturing of the corresponding ICs — have considerably reduced interest in the global bulk approach based on SiGe layers.

A novel way to induce a "local" compressive strain in the channel of a PMOS transistor, using a so-called "recessed source/drain" method was presented at the 2003 IEDM.⁵ Selective SiGe epitaxy was used to replace silicon material removed from the source/drain area in a preceding, self-aligned etching step. Because of their larger lattice parameter, SiGe layers are compressively strained and induce an identical type of strain into the channel's adjacent silicon material. In that case, the strain is uniaxial instead of biaxial, as in the global approaches. Uniaxial strain has been reported to be effective in increasing carrier mobility. SiGe layers with a germanium concentration of 17% are known to increase PMOS drive current by 25%.

Compared to blanket epitaxy, selective epitaxy is much more demanding because it requires the control of additional critical factors such as the selectivity itself, as well as various loading effects that can modify local growth rate and dopant incorporation. Both depend on the size of the exposed silicon area and can reach a "loading factor" as high as two to three for the growth rate and three to 10 for the dopant concentration. However, pattern sensitivity can be controlled to a large degree by carefully adjusting key process parameters and gas flow dynamics.

Conversely, selectivity can be controlled by adding a suitable amount of HCl to the main gas mixture, and is further enhanced at reduced pressure. In addition, unwanted faceting and lateral overgrowth can occur, which can be minimized by a delicate temperature and pressure adjustment of the epitaxial process. As for blanket epitaxy, the pre-epi cleaning steps aiming at the native oxide's removal are also critical to obtain good crystal quality.

However complicated the final adjustment of the process parameters can be, a well-controlled selective epitaxy process can be developed that will meet the stringent requirements of high-volume manufacturing.⁵

The Smart Cut layer transfer process, as developed by Soitec, has been proven to be one of the most efficient and flexible ways to produce high-quality silicon on insulator (SOI) substrates. The first approach taken to make a strained silicon layer on insulator substrate used a strain-relaxed SiGe substrate as the donor wafer. By transferring a thin layer of SiGe to the handle wafer, an SGOI substrate is created on which a subsequent thin, strained silicon layer is grown by epitaxy.⁶ However, SGOI wafers present the same drawbacks as their bulk counterparts because of germanium's presence. Recently, germanium-free SOI wafers (also called sSOI), were introduced for the first time in 300 mm by Soitec and ASM.⁷ In this scheme, the strained silicon layer is transferred from a donor wafer that already consists of a strained silicon layer grown on a strain-relaxed SiGe substrate. It was demonstrated (Fig. 1 ) that the silicon strain is not only fully maintained during the layer transfer process, but also when the sSOI wafer is submitted to a thermal treatment that far exceeds that of a typical CMOS process.

1. Raman spectra showing the retention of a substantial spectral shift toward bulk silicon (left) comparing an as-grown donor wafer and a completed sSOI wafer (the shift of the SiGe layer of the donor wafer is shown as well). The shift represents a strain of about 1.2 GPa. Stability of the Raman shift (right) for a 20 nm sSOI layer after heat treatment at the indicated temperatures for 30 minutes. (Source: Soitec/ASM)

Special epitaxial processes have been developed that have enabled the production of sSOI wafers as thick as 70 nm without loss of strain or strain uniformity (Table ). With these new thick sSOI substrates, it is now possible to bring the advantages of strained silicon to partially depleted SOI technology.

The CMOS process used to make devices in sSOI wafers was adapted to accommodate the fact that the strained silicon layers were <40 nm in thickness. This means that devices with channel lengths greater than ~120 nm operated in the so-called "fully depleted" mode. I_off-I_on data for long channel NMOS (Fig. 2 ) show a 75% improvement in I_on. This is caused by a substantial band splitting of conduction bands, which promotes the population of electron states with light effective masses and reduces intervalley electron-phonon scattering.

2. Ion vs. Ioff for 2 µm wide and 2 µm long NMOS devices on SOI (blue curve) and sSOI (red curve) substrates showing a 75% improvement for the sSOI substrates. (Source: Freescale/Soitec)

Analysis of total device resistance as a function of channel length (Fig. 3 ) showed that the apparent decrease in performance enhancement with decreasing gate length results from a large fixed resistance external to the channel. The difference in slope between SOI and sSOI NMOS devices indicates that the strain-induced, channel-resistance reduction is 45%, and is maintained at the shortest channel lengths of 40 nm, confirming that strain in these small finished devices is maintained.

3. Total device resistance as a function of channel length for SOI (blue curve) and sSOI (red curve) substrates. (Source: Freescale/Soitec)

A small degradation in PMOS I_on is observed, because the strain-induced valance band splitting is smaller than that of the conduction bands. This, plus the quantum confinement-induced splitting (which has the opposite sign of the strain-induced splitting), leads to a net degradation in PMOS performance at moderate biaxial strain levels.⁸ It appears that, for PMOS performance improvements, a "local" solution as described above, but integrated in an sSOI wafer, might be suitable. As a first step toward this challenging solution, the integration of local strained silicon in SOI, rather than sSOI, is now described.

SOI wafer integration of local strain by selective epitaxy requires special attention to the etching and epitaxial processes. The reason is that the residual silicon must be as thin as possible to obtain the maximum amount of strain in the channel. At elevated temperatures and exposure to hydrogen gas, the exposed surfaces' silicon can migrate and change the profile of the recessed source and drain areas, especially when the residual silicon thickness above the insulator oxide is very thin. Therefore, the epitaxy process' temperature budget must be reduced, which calls for extreme control of the reactor integrity and gas purity to avoid degradation of the epitaxial layer's quality.

Satisfactory control of the epitaxial process can be achieved, however, as demonstrated in Figure 4 . This TEM graph shows the high degree of structural integrity of the resulting SiGe epitaxy, even for a residual SOI thickness of <10 nm. An extensive performance analysis of this 45 nm architecture has been submitted for publication elsewhere.⁹

4. Cross-sectional TEM micrograph of selectively grown SiGe in recessed S/D areas etched of a thin SOI substrate. The SiGe epitaxial layer is strained and induces a compressive strain in the adjacent channel. Also shown in this graph is the elevation of the S/D, which serves as sacrificial silicon for subsequent silicidation. (Source: Freescale/ASM)

The TEM graph also shows the elevation of source and drain for which the same epitaxial process was used. Such elevation facilitates subsequent silicidation that is required to lower access resistance. Next to mobility, series resistances, including contact resistance, are parameters of critical importance to increase drive current.