Paul Lindner, CTO, EV Group

Paul Lindner (Source: EV Group)

Paul Lindner is vice president and CTO at EV Group (Schärding, Austria). He has more than 15 years of semiconductor industry experience, and his past work has involved many aspects of semiconductor and MEMS equipment manufacturing. Lindner started working at EV Group in 1988 as a mechanical design engineer, where his responsibilities included the design of semiconductor processing systems and tooling for custom applications. Some of these were system designs pioneered in the first commercially available wafer bonders, SOI bonding systems or precision alignment systems for 3-D interconnect applications. Before becoming CTO, Lindner established a product management department group and was involved in marketing, sales, manufacturing and on-site process support. Lindner's current responsibilities include new technology development by heading product, project management and process technology departments, which consists of all process development work in EV Group's cleanroom facilities worldwide. EV Group provides wafer processing equipment for MEMS and microfluidics, advanced packaging, compound semiconductors, SOI, power devices and nanotechnology.

SI: Has the CTO's role changed from what it used to be, say, five years ago?

Lindner: Most certainly. Now, more than ever, a CTO must track new developing technologies — far more than he had to back then. He must be much quicker in deciding which will be the ones that will make it to industrial application. This is what I see as the CTO's principal task today. It fits with our corporate slogan: invent, innovate, implement. Between these three phases, there is a 10-year development period. SOI is a good example; we began studying it in 1996. So I'm constantly asking myself which of today's new technologies will be of use to us in 10 years.

SI: Speaking of keeping track of technologies, for years we've all looked to the ITRS as the technology compass. In your opinion, how useful is it?

Lindner: I see it in a twofold fashion: It strikes me as being too aggressive in the scaling area and too conservative in the employment of new technologies that might prevent that scaling; 3-D interconnect, for example. They have a global wiring brick wall for 2010 in the roadmap, although we could probably implement that technology now with very high yields using current <30 nm design rules, and gain the benefits to be found in aggressive scaling in the 65 or 45 nm node. We shouldn't blame the roadmap too much for this — by nature we're a conservative industry.

SI: Are you planning any changes for EV Group's technology map?

Lindner: We've established our roadmap to bring in new technologies. It includes new materials — SOI and strained silicon — and new system architectures — mainly 3-D interconnect, precision-aligned wafer-level bumping, and chip-to-wafer bumping. We supply equipment for both these technologies, and have a roadmap for future equipment needs in the areas of strained SOI. We know what will be needed equipment-wise to support this, and have established plans to implement it.

SI: How far does your roadmap extend?

Lindner: About five years, depending on the technology. With the way things develop these days, it is pointless to attempt to look beyond that.

SI: Is part of your roadmap based on the ITRS?

Lindner: Some. But our path is more aggressive. We're looking at technologies that will require changes from the CAD system onward, as in the case of 3-D interconnect. Considerable industrial R&D is required before one is fully able to implement a new technology.

SI: You've added to your Arizona and New York research facilities. How will you use them?

Lindner: We've expanded our U.S. operations by moving the headquarters from Cranston (R.I.) to Phoenix. We have taken over the building that used to be Motorola's FPD headquarters, and established an 1100 ft² Class 10 cleanroom. It's an impressive facility that also provides considerable office space for future expansion. To be close to key customers, we've also opened an office at the Albany Nanotech facility.

SI: What is your R&D philosophy?

Lindner: Being a medium-size company, we're precluded from doing basic research. What we do in the way of R&D must be very focused, and is typically done in cooperation with one or more key customers. This is especially true for new technologies, with customers such as Soitec, where we've installed new systems. Customers like that are our equipment development partners. Our R&D direction is based on what we get from carefully listening to customers, examining market needs, and taking a broad view of where a specific technology is headed and what's required to then crystallize all this into a product that will satisfy market's requirements. Almost all of our entire R&D effort is customer-driven.

SI: What are you doing in the area of MEMS and nanotechnology?

Lindner: We're the MEMS industry's leading equipment supplier. It's what has made EVG successful from the 1980s to the 1990s. It is still a 40-50% portion of our revenues. It is maturing, and certain aspects of MEMS technology developed by us have entered mainstream production (as in wafer bonding) and are being used. I don't see much of a link between MEMS and nanotechnology just because of feature size. Yes, there are microfluidic devices where nanotechnology is applied, but the device itself is based on micromachining techniques rather than on nanotech. Our nanotechnology involvement is with next-generation lithography methods based on imprinting soft lithography — something still mostly taking place in academia. We're seeing applications for nanotech producing <100 nm features not in microelectronics, but rather in mass storage applications, biomedical, etc. — applications where even state-of-the-art step-and-repeat technology cannot do the job.

SI: Processes and materials are being introduced at a rate that would have seemed impossible five years ago. How do you view this challenge?

Lindner: The variety of different materials that are, really, not compatible within an IC has greatly increased. Silicon, silicide, polysilicon, aluminum — all these materials fit well together. Today it is copper, low- and high-k dielectrics, metal gates, and so forth. I believe that the hurried introduction of so many new materials often contributes to the low yields we see sometimes mentioned in the literature. It would be nice if the industry could integrate these at a somewhat slower pace.

SI: From a device maker's perspective, what is the biggest challenge that we face today?

Lindner: We're involved in designing with SOI, which is supported by CAD programs. However, designing for 3-D interconnect is something that must be addressed. MIT has developed its own CAD software to do stack interfaces. You must realize that it isn't only the chip itself that must be taken care of; there is also the layout of the chips on the wafer, runout errors, how the edge is engineered so that two wafers will perfectly fit together and form a 100% bond without wafer-killing small unbonded regions at the edge. The 3-D challenge must also be addressed through design and process optimization.

SI: A majority of companies today believe it's impossible to develop new technology without partnering with someone. How do you view this?

Lindner: Large consortia put together to develop a technology can slow things down. Decision-making becomes trickier, and it remains to be shown that the extra time spent in making those decisions makes for better ones in the end. It sometimes puts me in mind of the old saying that a camel is a horse designed by a committee.

SI: What effect do you think offshoring has had on the industry?

Lindner: I believe that it is a dangerous practice because, although it begins with the outsourcing of manufacturing, it leads to the outsourcing of know-how. It is very challenging to develop technology in one country and manufacture it in another. You must have some manufacturing close to where development is occurring, to at least verify your processes. And manufacturing verification means producing millions of devices; otherwise, it's of no value.

In my view, from an equipment manufacturer's perspective, there is no benefit in moving your manufacturing overseas — especially when dealing with new technologies, it is better and more practical to have everything under a single roof. From an engineering perspective, with offshoring there is a risk that the feedback loop from manufacturing is no longer closed. Without this, design for manufacturability becomes more difficult.

The other risk that I see is that offshore manufacturing facilities sooner or later start their own R&D spin-offs and become independent. This has proven to be especially true in Taiwan and China. This, of course, impacts the U.S. engineering profession more than it does Europe, because it hasn't had such a focused semiconductor-related electronic engineering tradition as, for example, has Silicon Valley.

SI: Do you have IP concerns?

Lindner: Whatever is manufactured somewhere else can also be copied there; besides, we require very fine machining of our parts. However, our decision isn't entirely driven by IP concerns. We don't face the challenge — like others — of having to produce millions of units.

SI: Is EVG planning any moves to Asia?

Lindner: Yes. Besides our subsidiaries in Japan and Taiwan, we're further enhancing our presence in China. The establishment of a customer support center in Shanghai is on the agenda for Q1 and Q2. We do some manufacturing in other countries — new member states of the European Union. This complements our vertically integrated structure in Austria.

SI: Are there any trends we should pay closer attention to?

Lindner: Wafer-level packaging that employs not only the simple flip-chip bumping, but also wafer-level bonds to produce something that has all the properties of a package — redistribution, protection from the environment, mechanical encapsulation, optical interface to the environment through a CCD chip. We see considerable potential growth there, but not much is said about it in the literature. I expect that these packaging methods, possibly fueled by high-volume requirements such as cameras in cellular phones, will bring prices down.