Verification System Compresses Mask Production Cycle

As the technology and the industry progress from 65 to 45 nm architectures, fabs are increasingly finding one of the major challenges that they face is the work and time required to verify masks enhanced with optical proximity correction (OPC), which are being used in production more and more — including for some back-end layers. OPC techniques very efficiently use a variety of non-printing features to compensate for optical proximity effects; however, this also has the unfortunate effect of multiplying the complexity of the mask. What once was a minor issue at the 130 or 90 nm nodes has now become a major, costly manufacturing and development hurdle.

As every design and process engineer knows, there are several points at which it becomes necessary to do verification. OPC-based lithography requires that chipmakers verify whether a design has correctly printed on the silicon. EDA verification and OPC modeling tools generate parametrically varying test structures and specify areas whose features are near the process limits. These test structures and other features must then be measured by CD-SEM systems, and the resulting data can then be used to further optimize the OPC model. This is a time-consuming process that often requires several iterations.

During their cycle of operation, EDA tools generate lists of thousands of unique verification sites on a wafer. These are either features on an input design pattern or test structures generated by the EDA software. Invariably, in order to minimize measurement error and determine defects resulting from marginal or incorrect application of OPC, the engineer finds that each site must be measured multiple times.

The output offered from the various EDA packages that are available today includes the required metrology location as well as the type of measurement. Up to now, engineers have had to spend considerable time and effort to manually construct CD-SEM recipes for each site. Figures have had to be corrected empirically, printed, tested, and then corrected again. Often, more than one cycle has been necessary before the desired results have been attained. Aside from the fact that this tedious procedure requires many engineering and CD-SEM tool hours, usually adding up to days or weeks, the problem has been that results can still be inconsistent; to add to the uncertainty, there are often human errors in the recipe development process.

Applied Materials (Santa Clara, Calif.) has introduced an OPC-Check system that is designed to automate the CD-SEM recipe generation process. Used with the company's VeritySEM metrology system, the new system has been proven capable of significantly reducing OPC verification time. Designed to receive measurement locations and an image of the surrounding areas directly from EDA tools, the OPC-Check system then automates the manual steps that would otherwise have been required, and creates a recipe on the SEM system by using proprietary aerial image simulation and unique pattern recognition technology. The tool comes equipped with specialized algorithms that automatically create a set of parameters that include a "measurement box" in the specified location, plus pattern recognition and auto focus zones within the field of view. The information is then processed by the system to automatically generate complete CD-SEM recipes.

Result analysis in OPC-Check showing an overlay of the CAD design (white line), image simulation by OPC-Check (green line) and the actual SEM image. (Source: Applied Materials)

Using the recipes that were generated by the system, the CD-SEM then acquires the capability to automatically measure each of the thousands of sites as soon as the wafer is printed. The images and measurements that are obtained are then uploaded back to the OPC-Check tool, which then carries out extensive analysis. This extensive data can then be used for model building, mask qualification, or process window characterization.

The system has the capability to automate what has otherwise been traditionally an elaborate manual procedure, eliminating the error-prone work while at the same time reducing OPC design verification time by up to 90%. This provides a considerable advantage, since were this done in the usual manual way, it could take up to two weeks to finalize just a single recipe. Now, since the information is loaded on the CD-SEM tool beforehand, as soon as the wafer is printed it can go into the CD-SEM where all measurements are done on the fly.

With automated CD-SEM recipe generation, OPC-Check acts as a bridge between design and wafer fabrication by connecting CAD data with on-wafer measurement, significantly reducing the cycle time for new mask development.