Reliability Hazards for 45 nm Interconnects

With the advance to 65 and 45 nm devices comes a number of yield and reliability issues associated with back-end integration. In a recent presentation at IEDM, Mong-Song Liang of TSMC (Hsinchu, Taiwan) outlined many of the expected failure mechanisms for copper and low-k interconnects at these nodes. He presented a methodology for prescreening the strength of dielectric/metal stacks in severe environments. Liang stressed the importance of systematically optimizing integrated modules with respect to physical, electrical, reliability and manufacturability aspects.

To achieve 15% RC reduction with each device generation, ~85% effective scaling of dielectric constant (k) is targeted using SiOC-based interlevel dielectric (ILD), with a k value of 3.0 to 2.2 integrated with SiC-based etch stop layers (k=3.0-4.5). Copper voids, believed to result from electrolyte breakdown of copper plating, play a vital role in electromigration (EM) and stress migration (SM) behavior. Meeting the EM/SM specifications also depends on selecting the appropriate etch stop layer (ESL) and optimizing the trench/via depth ratio, factors that simultaneously impact the effective k (k_eff).

The Figure compares a unit process-driven development approach with an integrated modular approach. In the latter, performance requirements and the packaging environment are considered simultaneously, and reliability specs for EM, SM and time-dependent dielectric breakdown (TDDB) are built into each module. Study of the simulated strain energy release rate for various ILDs, damascene stacks and molding compound materials revealed that crack stopping force, defined as the release rate difference between critical strain energy and strain energy, tracks well with k_eff. Replacing lower metal IMD with SiO₂ or adjusting trench and via IMD thickness can improve the crack stopping force. Molding compounds with lower stress and lower thermal expansion coefficients also play a role in strain energy management.

Conventional, unit process-driven development flow vs. an integrated modular approach that considers reliability issues in each stage of development. (Source: TSMC)

Some of the yield and reliability issues inherent to the copper/IMD/etch stop stack include copper corrosion at the via bottom, which can lead to SM failure; CMP damage, which can cause line/line leakage and TDDB; and etch/ash damage of the ILD, which causes barrier discontinuity. Overall matching of film properties, including mechanical, chemical and interface specifications, is important to copper/low-k stack integrity and reliability. CTE mismatch, poor adhesion and high tensile stress can cause cracking along the copper/barrier/IMD interface. Damaged IMD layer or a weak interface with the etch stop layer usually causes intermetal leakage and abnormal TDDB, according to Liang.

Dielectric etch of the via and trench is generally performed in a single-chamber system, first using high-power, low-pressure, polymer-rich chemistry for IMD/ESL selectivity, then a lean chemistry at low power for the trench etch. To minimize porous low-k damage, etching with lower dissociation of ions and radicals is recommended, along with optimization of the in situ ashing scheme to reduce carbon depletion.

The TaN barrier preclean step is critical, as it cannot damage the underlying copper or adjacent via sidewalls. Via resistance and EM lifetime are directly impacted by preclean efficiency, with resistance being less sensitive than EM to an insufficient preclean. In the case of an overly cleaned surface, both via resistance and EM are degraded because of potential CuH_x formation. The preclean also affects barrier and dielectric adhesion, especially for porous dielectrics.

The copper plating process for 45 nm requires excellent bottom-up fill, and direct copper plating on barrier is suggested to avoid top overhang of PVD copper seed. Tuning of chemical components in the electrolyte leads to lower copper hump height, which relieves the burden on CMP. Post-ECP anneal has a strong correlation to SM. Inhibitor addition during polish and post-clean can help prevent copper corrosion.

The CMP step must be optimized to prevent film and stack delamination, as well as scratches and other defects. Low-downforce and low-friction CMP is key, as is slurry selection. A slurry with soft organic spheres combining an inorganic composite abrasive with monodispersed particle size distribution in a distinct pH domain allows excellent local and global planarization. The composite slurry provided an order of magnitude reduction in metal density dependence of intra-die sheet resistivity vs. a conventional alumina slurry.

For additional information on yield management, go to www.semiconductor.net/yield