FinFETs Used in Smallest Non-Volatile Flash Memory

Scientists at Infineon Technologies AG (Munich, Germany) have built the world's smallest non-volatile flash memory cell using finFETs. With gate dimensions measuring only 20 nm, the new memory cell would make non-volatile memory chips with a capacity of 32 Gb possible within a few years. That is 8× the capacity of what is currently available on the market.

Non-volatile flash memories are becoming increasingly popular as mass storage media for devices such as digital cameras, camcorders and USB sticks. The most advanced non-volatile flash memory devices available today can permanently store one or two bits of information per memory cell without a supply voltage.

The International Technology Roadmap for Semiconductors (ITRS) notes that future high-density flash memories for standalone data storage applications require devices with minimum feature size F smaller than 50 nm. To achieve that, Infineon researchers used a three-dimensional transistor device called the finFET, so named because part of the structure sticks up like a shark's fine (Figure ). By wrapping the gate electrode around the gate dielectric, this type of device provides greater control over carrier flow and leakage current. When used in memory devices that rely on oxide-nitride-oxide (ONO) charge trapping, such as the Infineon flash memory, finFETs have promising scaling behavior because of the improved electrostatic control of the channel region, note the researchers in a paper presented at the International Electron Devices Meeting (IEDM) in December.

Infineon demonstrated a 20 nm finFET-based non-volatile flash memory where the ultranarrow fins are only 8.5 nm wide.

Infineon said it has shown the finFET to be extremely durable with excellent electrical characteristics. For example, the most advanced memories on the market today need ~1000 electrons in order to reliably remember one bit. The new Infineon memory cell uses just 100 electrons; an additional 100 electrons stores a second bit in the same transistor.

The electrons that carry the information in a nitride layer lie electrically isolated between the silicon fin and the gate electrode. Just 8 nm thick, the fin is controlled by the 20 nm-long gate electrode. To keep word line and bit line pitch close to 2F and 3F even for the shortest gate lengths, ultrathin TEOS spacers of 12 nm were used, along with ONO layers with the smallest possible physical thickness still enabling large threshold voltage shifts for multilevel ability and good retention.

In the IEDM paper, the Infineon researchers described that with ultranarrow fins, <8.5 nm wide, ONO memory cells are scalable to at least a 20 nm gate length. The silicon fins in (110) orientation are fabricated using e-beam lithography, TEOS hard mask, resist trimming and dry etching from weakly p-doped Eltran OI wafers with an initial silicon thickness of 50 nm. After a sacrificial oxidation, an RTA tunnel oxide of ~3.2 nm is grown in a diluted N₂/O₂ atmosphere. The thicknesses of the LPCVD trapping silicon nitride layer is 6.5 nm, and the thermally grown blocking oxide is ~5.5 nm. Finally, in situ phosphorous-doped n+ gate polysilicon and a TEOS hard mask are deposited and patterned by e-beam lithography and dry etching, yielding a gate length of 20 nm. After depositing a TEOS spacer of 12 nm, the source/drain regions are arsenic-doped with a dose of 5 × 10¹⁵/cm² and RTP annealed.

The promise of finFETs and other types of 3-D transistors, such as the omega FET and Intel's tri-gate transistor, was recognized several years ago. At the 2002 IEDM, success with 3-D transistor structures was reported by IBM, AMD and TSMC. The approach is somewhat radical in that CMOS devices are typically built horizontally (i.e., they are planar), while finFETs are built vertically. However, chipmakers have so far figured out ways to fabricate devices such as the finFET with minimal deviation from standard CMOS processes, although tall narrow fins could still create a patterning challenge at very small dimensions.

Editor's note: One misnomer that has been propagated is the use of the term MUGFETs (multiple gate FETs) to describe these devices, helped in part by Intel's use of the term tri-gate to describe its architecture. It would be more accurate to describe them as multi-sided gates, since the gate electrode is continuous and the transistor remains a three-terminal device. On the other hand, some companies, such as Motorola, have demonstrated true double-gated transistors, where each of the two gates is independently controlled, making the transistor a four-terminal device (see "Organic Devices on Flexible Substrates Advance ," Semiconductor International, November 2004, p. 28).

For additional information on wafer processing, go to www.semiconductor.net/wafer