Ted Vucurevich, Cadence Design Systems, CTO

Ted Vucurevich (Source: Cadence Design Systems)

Ted Vucurevich is a senior vice president, office of the Chief Technology Officer at Cadence Design Systems Inc. (San Jose). He is responsible for driving advanced R&D and directing Cadence Laboratories. He also serves as an executive fellow. Before, as chief architect at Cadence, Vucurevich helped develop the strategies and technology initiatives in SoC-based design, DSM infrastructure, software interoperability, design methodology development, and Internet-based electronic system design. Vucurevich received his BSEE from the University of Arizona. Cadence is the world's largest supplier of electronic design technologies and engineering services. Its products and services are used to accelerate and manage the design of semiconductors, computer systems, networking equipment, telecommunications equipment, consumer electronics, and other electronics-based products.

SI: Particularly in a company like Cadence, what does the CTO bring into the mix?

Vucurevich: We have an office of the CTO that I share with Aki Fujimura, CTO, New Business Incubation. Our responsibility is to evaluate emerging technologies and forward-looking trends in the semiconductor industry at large, as well as in the systems space. We then distil from those trends a set of directions in which we should invest either technically, from a review perspective — a market analysis perspective — and consider issues that we would consider as disruptive. This business intelligence, in the normal course of working with our customers, gives us what I call the "18-month window view" to try to determine and project those trends beginning to form on the horizon and beyond. Our time horizons fall into three specific domains: one is the short-time domain, which has more of a consultative role — that is 0 to 18 months. We take that context and, working closely with our business units' product owners, use it to make short-term decisions that will give us the most flexibility regarding what might come next.

In the 18-36 month space (about two process generations out), we look at technologies engineered to solve problems that will exist two semiconductor process generations out. Increasingly, in the implementation space, once you get to RTLs, you are faced with the decision of going into single chips or multiple chips, for instance, which requires new design, analysis, and implementation tools to be created. We look those two nodes out, because that is historically where trends for potentially disruptive issues begin showing up. Two process nodes out, there already is enough research to provide a good idea of what designers want to execute. So the CTO is responsible for looking at that opportunity space for investment, and help decide whether we should try to put resources in place internally or externally.

The longer-term horizon is covered by our research activities. I believe we're the only major EDA company with an actual research lab targeted to the 36-month-plus time horizon. We use it to leverage our understanding of what is happening in the research community, through networking and connections, and to focus on specific areas that may have the capability of changing the game relative to what we are doing now.

SI: For years, we've looked to the ITRS as an indicator of technology developments and requirements. Do you find it equally useful in your planning?

Vucurevich: As an industry general trend indicator, it's quite good. It is somewhat conservative, however. All the modifications and updates to major plan revisions have always increased the rate at which we thought something was going to happen. It has had greater success in outlining trends for semiconductor processing and manufacturing. It's useful to see where the red bricks are. However, the design information is considerably more speculative — basic trends in microprocessor density, standard cell library density, interconnect width, power — those are all useful, but don't tend to be strong indicators towards the investment direction, related to what one should do. Here the ITRS isn't as useful for us, in terms of what we get out of querying our customers, and what they see as trends with their customers and various evolutionary matters. Obviously, a government standard requiring digital TV receivers by a certain time means that many will execute new designs to compete for the business that will result. Those are more specific trends, firmer requirements for design than what we see in the ITRS. We're at the crossroads: Certainly, it is something that we must look at, from a trends perspective in the fab, semiconductor space, but, because we are in the middle of what they do and produce and what design teams do, we must look at design trends in a more detailed fashion than the ITRS does.

SI: Design software has been instrumental in getting the silicon circuit to where it is today. However, now the design challenge comes from the sophistication level it is going to have to provide in incredibly complex architectures. How do you see this from your perspective?

Vucurevich: We should be able to continue down to the 65 nm process node — maybe stretch it to 45, although I'm doubtful. With the current way we describe what is manufacturable, the difficulties we're having is that what we manufacture is becoming increasingly complicated. We need what I call a POE modeling of the process — that is, process optical and electrical characterization of what is manufacturable. Today, those different types of process modeling tend to exist in their own unique form. For example, if I talk about what I can manufacture from processing and lithographic perspectives, those are typically translated into geometric rules. If you look at what has happened to the explosion of geometric rules required to specify a 65 nm process, for example, it's jumped some order of exponent, maybe squared in proportion to the complexity. This is because you have a process, such as CMP, and optical, such as the subwavelength lithographic effect, interacting with each other in non-obvious ways. This results in an explosion of localized rules attempting to describe what is manufacturable and what can be imaged — an attempt to describe every possible pattern through a simple set of rules to describe them. I don't think that will scale.

We must move towards a more model-based representation of what that manufacturability is. This has enormous implications for tools and technologies, because what those models must do is impedance-match what you can manufacture and what a design tool needs to produce as output. Over the next few years, we'll evolve towards a new way of representing manufacturing rules to integrate those different views. I understand the trade-offs in pushing a lithographic rule and what that means, for example, as a trade-off in the electrical space — is that I cannot get that information today. This will lead to new ways for us to hide the complexity that's becoming difficult to represent in the current way; for example, the design rule. We'll be able to hide that from the designers, because now the tools and what can be done in the process will have a more appropriate way of describing the trade-off. Placement or routing optimization will have a richer view of what is possible, and yet that view won't necessarily be represented as more complexity for those trying to describe the process or do the design.

SI: How will you cope with signal integrity concerns at those geometries?

Vucurevich: This is an example of what I referred to with the POE modeling requirement. To get the parasitics right means that I must do much more detailed analysis not only of the net, but also of its local neighborhood — and that neighborhood is three-dimensional. You track left and right — if it were a vertical line — as well as one and perhaps two metallization layers above and below. So you need a parasitic extraction and modeling technique that's scalable to chip level, with the accuracy to describe what's happening in the local neighborhood, which increasingly resembles a continuous interconnect model.

As chips increase in frequency, features that classically are extracted as lump RC models will tend more towards a distribution — a transmission — line. Typically, you use a field solver or something similar to extract the value. To get beyond this, you need a modeling technique that deals with the complexity of both low- and high-frequency elements. We have technologies that will allow us to do those extractions using statistical analysis and optimization, coupled with machine learning based upon a large set of patterns representative of the types of local environments that may be present in a chip. We then use these statistical techniques to combine the contributions of characterized patterns to predict what the actual pattern of a particular design will produce in terms of parasitics. This gives accuracy and scalability. It's these kinds of techniques that'll allow us to go subwavelength — 45 nm with immersion, with a 193 nm light source — and push the envelope with regard as to what the image will look like even with strong OPC correction, compared to what was drawn.

SI: It is at least an order of magnitude more difficult to design in 3-D, but it must be addressed. Is 3-D design relief on the way?

Vucurevich: It'll happen in steps. First, we must address the problem with tools and technologies that integrate to solve to the SiP problem. What we'll begin seeing is tools that will help validate the partitioning of the design into multiple pieces. Even in full 3-D, we'll have the issue of each plane of integration; what function am I going to put there? Many of the issues circle around how to decompose it, and once the decomposition is in place, how to test each individual piece as it is processed. And, when there is a problem, how do I effectively diagnose and trace it to its source? Then, we'll have to deal with the reliability issue — if one of the things that have been partitioned fail, do I have to throw the entire integration away, or is there a way to do local self-repair to some extent like we do in memory? There's still considerable learning that must take place regarding what I call the distributed chip before we can begin looking at the vertically integrated chip.

SI: Inexorably, the industry is progressing toward nanotechnology, which requires that many of the traditional ways of doing things be discarded. How are you preparing for this transition?

Vucurevich: Much of what's being done with new materials today tends to be radically different from "traditional" electronic systems. Right now, we're watching the trends, looking at applications, and asking ourselves what do we do now in our current discipline that has application to these new areas of material use? These early uses of new materials tend to be simple in design. The complexity comes in the manufacturing of something like the light antenna just produced using carbon nanotubes. However, when you consider this, what they have produced is just a new type of antenna — essentially a very simple element compared to a system. Thus, the first set of applications that people are trying to do with new materials tend to be simple. The Lego blocks have changed, not how they're put together. The design of systems is far in the future. By the time we reach that complexity, we'll not be dealing with standard cell libraries as basic building blocks for system design. It'll be the integration of subsystems that we'll be considering, and these subsystems will be extensions of components in existence today.

SI: What will be the design software provider and device maker's biggest challenges over the next five years?

Vucurevich: Working together to describe what they can build and what we can optimize, as engineers try to send designs through the fab. The way we describe the process today will be insufficient. Neither side has the answer today — it'll be a collaboration.