Higher Yields With Trench-First BEOL

In back-end-of-line (BEOL) processing, important changes include the replacement of low-k dielectrics with ultralow-k dielectrics and the non-linear increase of copper resistivity with sub-100 nm scaling of interconnect dimensions. In a recent paper presented at the International Electron Devices Meeting (IEDM), the Crolles, France-based joint venture between STMicroelectronics, Freescale Semiconductor and Philips Semiconductors demonstrated a fully integrated 300 mm, 65 nm BEOL that employed a trench first with hard mask (TFHM) dual-damascene approach. This strategy allows faster yield ramp because of better compatibility with low-k materials and improved lithography process window. The group was able to reduce the time-to-yield performance from 18 months to 7 months between the 90 and 65 nm nodes. In a second paper by Philips Semiconductors, STMicroelectronics and CEA LETI (Grenoble, France), the group showed that ALD barriers of TaN demonstrate better RC delay and reliability behavior than PVD TaN in the sub-100 nm regime.

Achieving copper resistivity <2.2 µΩ-cm at linewidths <100 nm is increasingly difficult because of the non-linear increase in copper resistivity caused by the increasing contribution of electron scattering on grain boundaries, interfaces and porous sidewalls. These resistivity increases can completely nullify the capacitive benefits of introducing low-k dielectrics. Therefore, the ratio of trench and via must be optimized for optimal RC performance (Table ), using appropriate circuit models. The TFHM approach used an OSG (k=3.0) or porous OSG (k=2.5) interlevel dielectric, covered with SiO₂, a metal hard mask, organic bottom antireflective coating and 193 nm photoresist. Process steps include:

• Line litho with organic BARC
• HM etch and via litho with organic BARC for line etch
• Via etch and resist ash
• Resist via fill and recess
• Line etch
• Resist plug ash and SiCN barrier etch

Because SiO₂ caps the low-k film, the low-k is not exposed to resist or BARC, preventing resist poisoning, which is a problem for via-first, trench-last approaches. This allows the use of a wider range of surface treatments, etch and stripping processes. Also, this scheme allows simple lithography rework with standard oxidizing plasmas. The effective dielectric constant (k_eff) was 3.3 for the OSG and 2.7 for the porous OSG. The transition from 90 to 65 nm is simpler, because the only process steps exposed to the new dielectric are etching and metallization — as opposed to lithography, which is more sensitive to process windows.

Even with severe via misalignment, via yield was high (>99% on a 25 million via chain, resistance=2.2 Ω/via). Process variability in via resistance and metal sheet resistance was minimized by an optimized CMP process, which landed in SiOC after hard mask and dielectric cap removal. Greater than 80% yield was achieved on a test assessment circuit based on a 65 nm back-end intensive design with six metal layers and a 76 million via inverter chain. Functionality of a 2 Mb SRAM vehicle was also obtained.

The second report explores the electron scattering effect through the construction of single-damascene copper structures etched in porous SiOC (k=2.4) with a CVD TiN hard mask spacer approach. The patterning process uses a binary mask with a large variation of line patterns ≥120 nm. After exposure, the patterns are transferred into a TiN hard mask. Next, the TiN CVD spacer is deposited conformally, then etched off the top layer, leaving TiN spacer, and then the porous OSG trench is etched. The etch and strip is optimized for pore sealing. Next, either a 3.5 nm ALD TaN barrier or a 15 nm PVD TaN barrier is deposited, followed by 80 nm copper seed, electroplating, anneal and CMP.

The line resistance of the ALD split lots was ~5% less than the PVD lots because of the thinner barrier. But the difference in copper cross-section was smaller than expected due to larger overpolish of the ALD lots, confirmed by TEM analysis and smaller capacitance for ALD lots. ALD outperformed PVD in terms of leakage current (indicating no absorbance of ALD precursor in porous film), smaller mean line resistance (caused by large copper volume in the line despite overpolish) and better RC performance (10%).

The plot of specific resistivity as a function of copper cross-sectional area of the line showed the non-linear contribution caused by surface and grain boundary scattering start to play a role below 100 nm trench widths. The narrowest line (50 nm) shows a 50% increase in resistivity, compared with bulk copper (1.8 µΩ-cm). Electromigration, leakage current, dielectric breakdown and bias temperature stress testing all showed superior results for the ALD lots. This indicates ALD will play an important role in keeping line resistance down in sub-100 nm lines and vias.