Printability Drives Yield at 65 nm

The ability to accurately print the image intended by the designer on the wafer is one of the greatest challenges at the 65 nm node. This is especially true given all the resolution enhancement techniques (RETs) that must be employed. In addition, with foundries and others going to so-called recommended design-for-manufacturing (DFM) rules to realize higher yields, designers are in need of tools to help them evaluate the implication of these relaxed rules. Designers also need to know how to assess the physical layout of the design so that feature fidelity can be preserved across the manufacturing process window, not just at nominal dose and focus.

Mentor Graphics (Wilsonville, Ore.), among other companies in the DFM space, is developing tools to address many of these concerns. "Over the next several years, RET products will go from an R&D curiosity and small market to a market that is one of the big three revenue sources for EDA joining synthesis and place and route," said Joe Sawicki, vice president and general manager of Mentor Graphics' Design to Silicon Division. "One technology that's going to have a major impact is the ability for the manufacturer to assess the application of RET and determine how the modifications are going to perform across the process window. Because different features in the design have very different optical context, there will be particular features that are more problematic, and if you know where they are and can handle them differently, you'll be able to get higher yields."

By identifying and verifying these weak post-RET regions, such as those shown in the Figure , corrective action can be taken before the mask is created. Verification technology is also driven by the combination of RETs being used today. "Techniques haven't been replaced but supplemented. So people will still do some rule-based OPC, add model-based OPC on more critical features, use sub-resolution assist features to help with the iso/dense bias problem, and the question comes in, How do I verify all this?"

A probability to failure report identifies the features least likely to print successfully through the process window — through focus and exposure dose. (Source: Mentor Graphics)

The next step beyond identification of potentially non-printing regions is the ability to send information related to sensitive areas to CD-SEM tools for efficient inline monitoring. A significant recent development in DFM has been the introduction of a new data format, Oasis, designed to replace the long-used GDSII data format that mask writers and pattern generators use to recognize design data. Oasis can not only handle much larger file sizes, but it has flexible property annotation so that it can communicate design intent downstream, such as feeding information to metrology tools or testers.

DFM recommended rules are being defined at 130 nm by foundries and IDMs to improve yields. For a minimum design rule of 110 nm, the recommended rule might be 150 nm. According to Sawicki, the current methodology does not provide information about adherence to recommended DFM rules and does not facilitate prioritization or trade-off decisions. Identifying violations of recommended rules across a chip leads to, for instance, 11,000 errors on a chip portion one-hundredth of a typical SoC. Mentor's new Calibre Measure identifies features that violate a DFM rule, and for each feature, calculates the degree of violation.

"It shows how many of these errors are right next to minimum spacing vs. ones that are close to the recommended rule. It gives the statistics graphically in Pareto plots so that features of the highest priority can be fixed first," Sawicki said. Rather than concentrating on 11,000 errors, the engineer is directed toward the 40 most yield-limiting.

The Calibre DFM Analyze allows the user to look at the cumulative impact of several yield-limiting features. It provides user-defined yield grading to determine the location of biggest opportunity by window or cell. Calibre Transition is a tool that evaluates the transitions between metal levels (via fidelity) and determines areas where yield loss is likely caused by poor overlay. It then inserts redundant vias without increasing the in die size.

In the test arena, in addition to random fault coverage, Sawicki said that directed fault coverage will be important as new failure mechanisms are identified at the 65 and 45 nm nodes. "We will be correlating design features to yield on the factory floor that allow us to drive off and determine the yield impact of a single via vs. a double via, pull together Pareto analysis that says which failures are driving most of the yield loss, and do product-specific yield enhancement through the test mechanism."