Dual Liner Stresses NMOS and PMOS

The semiconductor industry has embraced strained silicon as an inexpensive and effective way to improve device performance and conserve power. Tensile nitride capping layers are already in production use to improve NMOS device performance, and now a joint project by AMD and IBM shows how it's possible to incorporate tensile and compressively stressed nitride contact liners in a high-performance CMOS flow to improve both NMOS and PMOS performance.

In work presented at the International Electron Devices Meeting (IEDM) in December, the two companies said the dual stress liner (DSL) approach results in effective drive current enhancement of 15% in NMOS and 32% in PMOS, and saturated drive current enhancement of 11% and 20%, respectively. Hole mobility in PMOS was increased by 60%, without the use of SiGe, which has been the focus of other strained silicon research.

This all equates to a 24% transistor speed increase at the same power levels, compared with similar transistors produced without the technology. Yield is also comparable. AMD and IBM say this makes them the first companies to introduce strained silicon that works with silicon-on-insulator (SOI) technology, resulting in an additive performance and power savings benefit.

In a press release, AMD said it intends to gradually integrate the new strained silicon technology into all of its 90 nm processor platforms, including its future multi-core AMD64 processors. In the IEDM paper, however, researchers said single- and multi-core SOI microprocessors are already being manufactured using the DSL process in multiple, high-volume fabrication facilities. They also note the technique is extendable to 65 nm CMOS.

AMD plans to ship the first 90 nm AMD64 processors using the technology in the first half of 2005. IBM plans to introduce the technology on multiple 90 nm processor platforms, including its Power Architecture-based chips, with the first products slated to begin shipping in the first half of 2005.

"Innovation has surpassed scaling as the primary driver of semiconductor technology performance improvements," said Lisa Su, vice president of technology development and alliances, IBM Systems & Technology Group.

The dual stress liner (Figure ) is formed after the silicide process. First, a highly tensile Si₃N₄ liner is uniformly deposited over the entire wafer. The film is then patterned and etched from PMOS regions. Next, a highly compressive Si₃N₄ liner is deposited, and this film is then patterned and etched from NMOS regions. Alternatively, the films can be applied in the reverse order. Subsequent process flow, including interlevel dielectric and contact formation, remains the same.

A new dual stress liner process employs a tensile nitride to improve NMOS device performance, and a compressive nitride to improve PMOS performance. The SEM cross-sections were taken from an SRAM cell fabricated with the process.

One of the challenges of the process is that the liner must be cleared from PMOS regions by an etching in the presence of the silicide. As a result, the silicide sheet resistance value in the exposed regions can be affected by the removal process. An "optimized" etch process was developed to maintain low-silicide sheet resistance.

The dual stress liner with SOI technology was developed by engineers from IBM, AMD, Sony and Toshiba at IBM's Semiconductor Research and Development Center (SRDC) in East Fishkill, N.Y., as well as engineers from AMD's Fab 30 facility in Dresden, Germany.

"This breakthrough in strained silicon engineering is a result of our joint-development alliance and the efforts of our partnered teams at IBM's facility in New York and AMD's facility in Germany," said Nick Kepler, vice president of logic technology development, AMD.

"Innovative process technologies such as strained silicon enable AMD to deliver more value to our customers," said Dirk Meyer, executive vice president, Computation Products Group, AMD. "Our shared progress in developing advanced silicon technologies allows AMD to deliver today's best performance per watt, and this strained silicon development is expected to extend that leadership when we begin shipping the dual-core AMD Opteron processor in mid-2005."

IBM and AMD have been collaborating on the development of next-generation semiconductor manufacturing technologies since January 2003.