2005 ITRS: The Year Ahead

2005 marks the 14th year of the International Technology Roadmap for Semiconductors (ITRS, originally NTRS). Thus, it is very close to "completing the first cycle" of its 15-year rolling horizon. Over this period, the roadmap has generally "accelerated" — i.e., most of the technology parameters now projected for 2005 are ahead of the targets set by the initial NTRS in 1992. Traditionally, we have summarized the overall pace of this technology advance in terms of the time gaps between successive "technology nodes." The intent of the technology node concept has been to select a single parameter best representative of the overall CMOS scaling trend.

In 1992, the original roadmap organizers (the Roadmap Coordinating Group) had a long discussion on the choice of such a parameter. During the first phase of the discussion, we agreed that some measure of the lithographic capability available to the industry at a given time would be the most direct indicator of scaling status. After abandoning attempts to define some "standard lab test" of lithography resolution, we agreed that a more practical measure could be simply based on the tightest features going into production on commercial ICs. Thus, the technology nodes came to be designated by the minimum half-pitch of interconnect on the most aggressive product (by this measure) beginning its ramp to volume production, with the time gap between successive nodes defined by ~0.7× scaling of this metric.

So far, DRAM has always been the volume product with the smallest interconnect half-pitch and, thus, has determined the pace of the technology nodes. However, in 2005, we are well into the SoC/SiP era, in which the drivers of IC technology are very diverse, and just getting into the "effective scaling" era, in which improvements in materials, devices structures, circuit design/architecture and manufacturing cost are at least as important in continuing the advance of IC technology/products as are further increases in lithography capability. Therefore, the technology node concept is rapidly becoming too much of an oversimplification of the industry state-of-the-art. This has been reflected in recent years by growing confusion reflected in various "ad hoc specific-product technology-node definitions" in press releases, conference presentations/publications, etc.

The simple fact is that the ITRS technology nodes were never intended to be a "yardstick" that could be directly applied to any specific product other than the one with the tightest interconnect pitch (e.g., DRAM) serving as a surrogate for the general lithography capability available to the industry. Of course, indirectly, it has always been appropriate to say that any product employing the same generation of lithography (and other) tools to their reasonable limits, given the additional constraints on layout, etc., for that product, is part of the same technology node as the "node-defining DRAM." However, in the past few years, this has not been the way that many people in the industry have been characterizing the "technology node" of their products. They have, naturally, employed individual node definitions that they feel are more meaningful to their products and that, in most cases, synchronize with their ability to introduce new "product technology generations" at approximately an industry-benchmark two-year pace.

Based on these considerations, we feel that the traditional, simple ITRS technology-node concept has outlived its usefulness. Therefore, one of our major goals in the 2005 ITRS is to provide a broader, more balanced perspective of the diverse drivers of semiconductor technology in the era of SoC/SiP and effective scaling.