Impressions of the 2004 ITRS: Progress and Wake-Up Calls

Every year about this time, the International Technology Roadmap for Semiconductors (ITRS) gives us a fresh glimpse at the future of our industry through a 15-year window of challenges and opportunities. In early December, the International Roadmap Committee (IRC) unveiled the 2004 Update of the ITRS at a press conference in Tokyo. While not a new edition of the roadmap (that happens every odd-numbered year), this update makes compelling reading, because it reflects the rapid changes that have occurred in the industry over the past year. Its messages are both hopeful and sobering, a mixture of good news for traditional CMOS scaling and wake-up calls concerning the need for new devices and larger wafer sizes.

With that said, here's my take on some of the more noticeable changes in the 2004 update, and how SEMATECH is addressing them:

The blueprint for optical has undergone substantial revision because of the emergence of 193 nm immersion and the consequent sidelining of 157 nm technology. The 2004 ITRS cites progress on conventional 193 nm tools using high numerical apertures (NA~0.75), along with systems that combine even higher NA and immersion. There needs to be considerable work to understand the extendibility of 193 nm immersion to 45 nm half-pitch. There have been some good advances in extreme ultraviolet (EUV), particularly related to source power and mask blank defects, demonstrating viability. Quite a bit of interest is being generated in maskless solutions (ML2), which still need to demonstrate feasibility.

As the industry realized that technical difficulties with 157 nm might delay its manufacturing introduction past acceptable dates, SEMATECH was a driving force in the emergence and validation of 193 nm immersion. Beginning in 2002, we organized a series of industry workshops focusing on driving solutions to critical issues that today have brought manufacturers to beta-level production and suppliers to the introduction of production-level tools. In 2005, we will focus on the limits of immersion lithography and determining the feasibility for 45 nm half-pitch and beyond.

In the EUV arena, a SEMATECH-sponsored workshop in Japan last November showed source power increasing to nearly half the level needed for commercial production (to 50 W at the intermediate focus), along with new efforts aimed at advancing the lifetimes of EUV collectors.

SEMATECH also is exploring the potentials for maskless lithography, notably by sponsoring an industry-level Maskless Meeting Jan. 17-19 in San Jose.

After many delays over the past decade, the development schedule has stabilized for low-k materials. Materials at an effective k (k_eff) of 2.7 are already in production, and compounds of k_eff=2.4 are expected to come into fabs within the next three years.

SEMATECH continues to help drive the industry's search for timely low-k materials. We now focus not only on understanding new low-k materials, but also on the process effects that result in higher k_eff, with modeling and techniques to solve these issues.

It's time for the industry to get serious about preparing for the next wafer size. Historically, new wafer sizes have been introduced about every 10 years, with 300 mm having gone into production in 2001. To maintain the historic rate of progress, the next size will be needed around 2010-11, and for productivity reasons, the mostly like candidate is 450 mm.

Given history and future productivity challenges, there's no time left to lose in deciding whether to introduce a new wafer size into the industry. Through our subsidiary, the International SEMATECH Manufacturing Initiative (ISMI), we are making the exploration of 450 nm wafer approaches a priority for 2005. ISMI is conducting a full-scale modeling study on the feasibility, economics and timing of 450 mm conversion. Results of the study are set to be delivered to ISMI member companies in spring 2005.

Design innovations aimed at ridding the chip of unwanted carriers of leakage current are already in production, or planned for introduction within the next few years. Strained silicon has found its way into manufacturing as a means of increasing transistor current and/or reducing leakage current, and its use will become more widespread. Meanwhile, high-k dielectrics and metal-gate electrodes designed to reduce gate leakage are expected to enter manufacturing at 45 nm. This is leading us into non-classical CMOS, which should allow the continuation of transistor scaling well into the next decade.

In conjunction with the AMRC, SEMATECH's Front-End Processes Division will deliver an understanding of the best high-k materials and metal-gate solutions over the next year. This effort includes projects in advanced-gate-stack electrodes, developing CMOS-compatible metal-gate solutions, and electrical characterization and reliability testing for high-k devices. A related project is exploring and developing infrastructure for non-classical CMOS structures, such as materials, unit processes and tools, to meet ITRS requirements. This work is aimed at providing robust, cost-effective manufacturing capability for FEP, and supporting continuous scaling to the 45 nm node and beyond.