Damage-Free Cleaning Beyond 65 nm

As the semiconductor industry develops processes for the 65 and 45 nm nodes, wafer cleaning faces new challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) requirements — including increased fragility of structures and materials, and more stringent requirements for cleanliness and material loss.
 
Although there will still be a place for standard cleaning chemistries and batch systems for non-critical layers, there is a call for innovative, novel techniques to provide damage-free cleaning for the critical areas. Dealing with potential megasonic or plasma damage will be key, as will finding new methods and chemistries to safely clean porous low-k materials without turning them back into high-k materials.
 
Little explosions
 
Megasonics has been used for many years to clean wafers, creating and imploding bubbles in the fluid to remove particles from the wafer surface. But megasonics has begun to cause problems, even at the 90 nm node, and can cause even more damage at 65 nm and beyond. "When features were more robust, that was acceptable," said Kevin McLaughlin, technical marketing manager for SCP Global Technologies (Boise, Idaho). "Now the amount of energy it takes to get rid of a particle is about the amount it takes to remove a feature from the wafer."

Polygate structuring is a key area that can be harmed by megasonics damage. At 65 nm, polygate lines are somewhere around the 40 nm range, and are very susceptible to megasonics damage and breakage, noted Harald Okorn-Schmidt, vice president of the Global Research Group at SEZ (Villach, Austria, and Mountain View, Calif.). "Most chipmakers stopped using megasonics at 90 nm technology already," he said. "They're doing stronger substrate etching instead." But that can lead to increased material loss.

SEZ conducted a study using sonoluminescence, which let the engineers better understand the relationship between megasonics, particle removal and damage (see "Sonoluminescence Helps in Design of Megasonic Cleaning System," p. 40). The mechanisms of megasonic cleaning send out light — mostly in the UV range, but also in the visible, Okorn-Schmidt explained. SEZ used this natural occurrence to measure how uniform a megasonic system is, thereby enabling them to influence the cavitation in the appropriate areas. "Megasonic cleaning has always been a black magic sort of thing," Okorn-Schmidt said. Now, with the amount of research the company has done trying to understand megasonic systems, he said, they feel that they really understand the basics of the system.

Convincing customers to once again trust megasonic cleaning to their fine features is a bit of a battle, though, Okorn-Schmidt said. "There are some parts of the world that are more concerned with megasonics because they burned their fingers harder. We're on the way to convert the industry back to believing in megasonics."

Megasonics offers the advantage of thinning the boundary layer, Okorn-Schmidt said. "When you get the megasonics right, you can improve particle removal and particle removal uniformity without creating damage."

Several cleaning system manufacturers are looking for ways to modify standard megasonics schemes to improve particle removal and decrease damage. One option to minimize damage is simply to go to lower and lower energies with the megasonics, McLaughlin noted. "That's OK, but you start reducing the amount of particles being removed. If that's the only knob you have to turn, eventually you just turn the megs off."

On the other hand, going to increased chemical cleaning — stronger, hotter cleaning solutions — can lead to other adverse effects such as surface roughness. "So you have to be pretty dilute, you can't be all that hot, if you use megasonics you're going to start damaging — you just don't have enough knobs to turn," McLaughlin said.

The key that the system providers are invariably turning to is single-wafer processing. "With single wafer, you at least can tailor conditions to one wafer rather than averaging those conditions over a batch of wafers," McLaughlin said.

While Tokyo Electron Ltd. (TEL, Tokyo), for example, continues to extend batch megasonics (improving uniformity of the power distribution in the batch systems), the ultimate solution for future nodes will be single-wafer processing, said Glenn Gale, surface preparation systems technologist at TEL. "To avoid oxide and silicon loss, some form of physical energy needs to be used. Fundamentally, single-wafer tools have an advantage in terms of being able to apply this energy more uniformly, whatever form it might take."

Although there are about as many different single-wafer schemes as there are cleaning suppliers, McLaughlin said, they're all geared toward tailoring conditions to a single wafer (Fig. 1 ). SCP's single-wafer immersion megasonics system places the wafer in the same orientation as it would be in a batch system, immersed in fluid. With three independent transducers, two side-mounted megasonics are directed not at the wafer surface, but rather up at the liquid-air interface. The technique then brings the wafer to the megasonic interface rather than bringing the megasonics to the wafer, enabling better control of the amount of contact time, McLaughlin said. "It's enough time to achieve particle removal, but not enough time and energy density to damage features."

1. SEM images of 50 nm polysilicon DRAM storage capacitors show the effects of megasonics within a batch immersion tool using high power densities (left, with extensive device destruction), and in a single-wafer chamber with multiple transducers (right, showing no damage). (Source: SCP Global)

"Most of the customers want to have a completely single-wafer fab. The wet area is one of the last areas to convert to single-wafer," said Heinz Oyrer, corporate planning director for the SEZ Group. "They're convinced about the economics and the flexibility, but now we have to add the technology. It especially makes sense for new fabs."

Some argue, however, that batch cleaning is not likely to become obsolete. Not every layer or device is so critical, and there are times when throughput is more of a factor, they say. "Everybody has to do a nitride etch step somewhere as part of their flow," McLaughlin noted as an example. "That's typically a 30-minute batch process. You wouldn't want to do that one wafer at a time."

Besides megasonics control, another major driver from batch to single wafer is the ability to minimize film loss, McLaughlin said. According to the International Technology Roadmap for Semiconductors (ITRS), silicon loss and oxide loss will need to be cut in half when moving from the 90 nm to the 65 nm node — from 1 to 0.5 Å. Single-wafer systems and their associated short process times are the way to achieve that, McLaughlin said. "If you can combine low-concentration chemistry and short process time, it is very achievable."

Film loss control is especially critical for chipmakers using silicon-on-insulator (SOI) technology, Okorn-Schmidt said. "They can't afford a loss of 10 Å." Some companies are trying very high etching for bulk silicon, he said. "Some, like SOI, are just living with less yield."

But cleaning companies say they can handle the film loss requirements at the 65 nm node. SEZ, for example, says it can clean 80% or more of the particles with zero damage and <0.5 Å oxide loss.

"Basically, there are trade-offs involving particle removal, oxide loss and pattern damage. We already know how to achieve 1 Å oxide loss or even 0.5 Å in a clean. The issue is whether particles can be removed effectively enough under such conditions," TEL's Gale said. "A way of achieving this, of course, is adding the physical energy of megasonics, but then the damage issue arises. Our approach for single-wafer cleans is to eschew megasonics and use a fine atomized mist spray for selectively removing particles without damage. We have been able to achieve very effective particle removal with only 0.5 Å oxide loss and no damage to polylines as small as 65 nm."

For many chipmakers, the substrate loss requirements set forth by the ITRS may not adequately address the problem, according to Ivan Berry, director of technology for the Cleaning and Curing Systems Division at Axcelis (Beverly, Mass.), and also a member of the ITRS Front-End Process Group. The ITRS quantifies the silicon or oxide loss based on polysilicon or thermal oxide, but it turns out implanted silicon or oxide are attacked much more rapidly than polysilicon or thermal oxide, he explained. "If you have zero loss in a typical measurement, when you go to a real structure, you can see substantial — in many cases unacceptable — losses on the surface."

Besides megasonics, chipmakers are also becoming increasingly wary of the damage that can be caused by plasma processes, commonly used today for photoresist strip (Fig. 2 ).

2. Photoresist strip is required at several layers throughout device processing, with high-dose ion implant strip presenting particular challenges. (Source: Novellus)

The most difficult FEOL resist strip is typically after high-dose ion implant (>10¹⁵ dose with energies >40 keV), according to Wilbert van den Hoek, CTO and executive vice president of integration and advanced development for Novellus Systems Inc. (San Jose). "During the implant process, the resist forms a crust on the surface," he explained. "This crust is a dehydrogenated carbonized film formed by energetic ions and heat from the implant process, the ion implanted species, and re-sputtered materials of silicon or silicon oxide from the wafer surface. This crust prevents outgassing of solvents from the remaining photoresist when the wafer is heated during the typical ash processes. The challenge for high-dose implant strip is to remove this crust at low temperature to prevent these solvents from building enough pressure to burst open the crust and showering the wafer and chamber hardware with resist particles."

Although there is some debate about what form of carbon it takes, it behaves chemically like a diamond-like carbon, and has a very high chemical bond strength, Axcelis' Berry said. The activation energy for normal photoresist in oxygen plasma is ~0.15-0.18 eV, so it's fairly easy to break the resist down, he explained. But with carbonized resist, the activation energy is more like 2.5-3 eV, making it inert in oxygen at reasonable temperatures. So the solution, of course, is to go to higher temperatures. "But if you try to raise the temperature to a point where you get reasonable activity, the photoresist starts to melt," Berry said. "As it melts, it loses structural integrity. With the stresses that occur (tens of GPa of stress), you get explosions on the wafer called 'popping.' This sprays particles all over the chamber and wafer, which isn't a good thing to do."

According to Berry, there are two common approaches to remove the carbonized crust layer without causing the popping event to occur: 1) Add fluorine to the chemistry, which enhances the chemical reactivity of the carbonized crust. 2) Add ion bombardment in the oxidation process, breaking the carbon bonds so they can react with the oxygen.

Although these solutions have worked since the 1970s, Berry said, the problem lies with current device generations and beyond, which cannot live with any measurable substrate damage. Ion bombardment causes sputtering, and fluorine will etch SiO₂. Berry used the stripping of photoresist from a source/drain region as an example: "When you do the stripping in, say, oxygen with ions, the ions combined with the oxygen are starting to oxidize the thin surface of the source/drain. You start consuming some of the implanted boron when the oxidized silicon containing the boron is removed, for example," he explained. "If you look at ultrashallow junctions — if you look at implant concentrations of the boron, most goes in at surface, and is rapid thermal annealed to make the junction. So any loss of surface causes significant loss of boron dopant."

The non-plasma approach to photoresist strip involves things like RCA, Berry said, which also consumes some silicon. So companies are looking for new ways to approach the problem. "We think we have a revolutionary approach to it, but we can't disclose it," Berry said. "Right now, it looks exciting."

For now, Axcelis and other companies are turning the available knobs on existing plasma strip systems, reducing temperatures and controlling ion bombardment. "It's working OK for now, but the next generation is going to be challenging," Berry said. "At 45 nm, something novel may come into the marketplace."

Although cleaners do not seem overly concerned about what lies ahead in high-k dielectric materials and metal gates, they do concede that low-k dielectrics are likely to cause difficulties. The challenge is removing photoresist at the BEOL, for example, without corroding the copper and without changing the k value of the dielectric materials, SEZ's Okorn-Schmidt said, noting that the low dielectric constant is very hard-earned. "If we go in there and introduce some OH functions, the constant goes up," he said.

If the low-k material gets damaged, and then subjected to a wet clean, the water reacts to form SiOH bonds, Berry said, creating very high dielectric constants. The low-k material becomes something like a high-k material, and becomes very prone to further damage in subsequent wet cleans.

It is particularly difficult to strip photoresist from structures incorporating low-k materials, Berry said. In common low-k materials for semiconductor production, the weakest bond is the bond between the methane and the silicon. "That's the bond you want to maintain the dielectric as a low-k dielectric," he said. "If you subject it to any energy, the first bond you lose is the bond you want to preserve."

Also, oxygen reacts rapidly with methane to form water vapor in CO, Berry said, so you cannot subject them to even moderate temperatures. The trick is figuring out how to remove the photoresist, which is a hydrocarbon. Berry mentioned a few approaches:

1. Use oxygen, but at very low temperatures to prevent rapid methal group loss. Use ion bombardment during the strip process (to react the photoresist with oxygen at room temperature or below), and use the anisotropy of ions to prevent the low-k material from facing ion bombardment. However, backscattered ions can create damage on the low-k sidewalls. The damage is typically limited to ~100 Å, which you'd rather not have, but which is much better than before.
2. Strip the photoresist with atomic hydrogen, or protons. The strip function is not quite as effective, but the chemistry reacts less with the low-k dielectric. But you still get 100-200 Å of damage because of the hydrogen.
3. Axcelis uses heat to thermally decompose the photoresist, heating the resist until it starts to decompose, then exposes it in an activated hydrogen environment. "From what we can tell, we can get zero low-k damage," Berry said.

Particularly challenging are resist strip and clean on the porous low-k materials (mostly carbon-doped SiO₂ films) slated for the 45 nm node, Novellus' van den Hoek said. "Conventional oxygen-based strip chemistries would remove the carbon atoms, causing a significant increase in dielectric constant and damage to the film structure," he said. "Alternative hydrogen-based strip chemistries need to be developed to strip ULK CDO films." Also, the pores of the high-porosity films can trap moisture, making any post-resist-strip wet clean difficult, van den Hoek added. "The challenge is to develop a resist strip process that would not need any post-strip wet clean processing."

High aspect ratios — whether tall or deep, FEOL or BEOL — present challenges for cleaning. Stacked capacitors, for example, are tall, narrow structures that are very subject to damage. Deep structures such as trench capacitors or damascene patterns make it more difficult to get the chemistry and rinse water in and out of the deep trenches. In both the tall and deep structures, drying has become a critical issue. In deep structures, you have to be able to get the fluids out without leaving watermarks, SCP's McLaughlin noted. Tall, narrow structures tend to try to stick to each other when drying, so stiction-free drying is important, he said.

Beyond the 45 nm node, in FEOL, device structures may include vertical transistors, such as finFETs. "In some of the vertical transistors, during cleaning processes, you have exposed active areas that get exposed to multiple cleans," Berry said. That's compared with now, where critical areas get cleaned once, maybe twice, he added. "You can afford less and less damage if it's getting cleaned multiple times."

If a resist strip process has excellent particle/residue-free performance, chipmakers may be able to eliminate the follow-on wet clean process step, van den Hoek noted. "Elimination of this wet clean step is an enormous cost savings to fabs. In addition, no wet clean is sometimes a technology requirement (porous low-k films as an example)."

"Certainly, both trench and stacked capacitor DRAM makers face tough challenges going forward," Gale said. "In the long term, unless the designers change course from simply increasing aspect ratio and packing density, these stacked capacitors could be the first area to run into a fundamental wall for liquid processing."