Polymer Pillars for Optical and Electrical Signals

There has been a fair amount of recent work on high-density optical interconnection between chips on a board, and even within a chip, to handle anticipated signal-density requirements. At the same time, the need for reliability under typical service conditions, low-cost processes, and compatibility with low-k die seems to conflict with these efforts. Researchers at the Georgia Institute of Technology (Atlanta) are developing a system of interconnection based on polymer pillars that may answer all these concerns.

Called sea of polymer pillars (SoPP), the process uses a spin-on photo- imageable polymer from Promerus (Brecksville, Ohio) that can be cured at temperatures below 200°C. Using i-line (365 nm) lithography and a spray-on development process on this negative-tone material, the group has demonstrated the ability to produce pillars <10 µm in diameter with aspect ratios >5:1 (Fig. 1 ). They have also produced ring-shaped polymer sockets using the same process.

The general concept is shown in Figure 2 . The pillars can be coated with metal and used as contacts to solder-filled sockets, optical waveguides that couple to planar waveguides using grating couplers or mirrors, or as dual contacts carrying both electrical and optical signals. Because the cured polymer deforms elastically, the pillars can flex in response to shear forces caused by thermal expansion mismatches or mechanical shocks without the use of an underfill. This also helps to maintain optical alignment.

1. The fabrication of pillars 250 µm tall and 30 µm in diameter (left), along with polymer sockets (right), using a photo-definable polymer has been demonstrated. (Source: Georgia Tech)

2. Polymer pillars can be used to carry optical signals, help make conductive connections, or both while aiding with alignment.

This is a relatively low-cost process that can be performed at the wafer level, and most wafer-level packaging facilities already have the required equipment. There is a trade-off in choosing the aspect ratio of the pillars between compliance and compatibility with processes such as wafer saw. When using pillars 110 µm tall and 55 µm in diameter, a wafer saw process involving high-pressure water did not damage the pillars.

The fact that these pillars can be fabricated with bakes at 100°C and cures at 200°C addresses concerns associated with low-k dielectrics on the die. Excessive temperature excursions can degrade some low-k dielectric materials, and they can hasten the rupture of barrier layers on the die that keep copper from migrating through the dielectric material. Keeping shear stresses away from the die also helps to keep these barrier layers from rupturing.

The polymer sockets can be made with positive slope sidewalls that can help with alignment during assembly. The hope is that die with polymer pillars can be placed into sockets using readily available pick-and-place equipment. This would represent a great improvement in manufacturing efficiency.

Mirrors or gratings are formed on the end of the pillars by imprinting the shape on the surface of the polymer before exposure. The group has demonstrated this using silicon imprinting molds. Molds of other materials, such as quartz, could also be used.

The group has also had success putting a Ti/Au (30 nm/1 µm) metallization on these pillars not only to provide electrical connections and mirror surface, but also to provide solderable caps and rings purely for attachment purposes. As shown in Figure 2 , the mirror metallization could serve a second purpose as a solderable surface to make contact with the substrate.

The work is still in its early stages, but if it fulfills any of its promises, it can enable the low-cost, high-bandwidth interconnection between chips that the International Technology Roadmap for Semiconductors (ITRS) calls for.

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