Testing Automotive SoP Devices

Electronics in automotive applications have undergone profound changes within the last few years. Cars today can have as many as 350 motors, each controlled by ICs to deliver more intelligent functions for power mirrors, light-source adjustments, automatic braking systems and more. Cost-reduction efforts and new emission standards drive automobile manufacturers to replace hard-wired switches and relays with semiconductors that combine microcontrollers, multiple communication busses and power-control components in a single package. There are new communication standards to replace and complement existing standards. Semiconductor manufacturers have started to prepare for a smooth transition to the 42 V board network, which is expected within the decade.

These trends drive the integration of power semiconductors together with microcontroller and communication technology to a complete new set of devices. This causes traditional power automatic test equipment (ATE) architectures to struggle to synchronize the digital and analog source and measurement capability across the entire instrumentation suite, resulting in increased test costs, added complexity and reduced test coverage.

Increased complexity and cost-reduction efforts will further drive electronic content and semiconductor integration in the cars of tomorrow. The cars today already have between eight and 10 subnets, a total of 50-60 network nodes, and an architecture where controller area networks (CANs) and local interconnect networks (LINs) complement each other. Figure 1 highlights today's automotive communication complexity.

1. Today’s cars have 50-60 network nodes and an architecture where CAN and LIN busses complement each other.

The new standards will drive digital content in conventional automotive devices, which causes digital pin counts and digital speed to increase over time. Therefore, it is important for the semiconductor vendor to select an ATE platform that has sufficient digital instrumentation performance in terms of channel density, repeatable time synchronization with analog instruments, and the ability to be configured single-ended or differentially. This becomes even more important if semiconductor vendors pursue a parallel test strategy in order to reduce test costs and increase the throughput per test cell.

The following example of a modern automobile door control unit shows how next-generation semiconductors allow the automobile manufacturer to save cost and weight. Today, most cars come equipped with automatic door locks, power windows and electrically controlled mirrors. To deliver all these functions, the door usually hosts a single control unit, which interfaces through a CAN interface with a central control unit. A heavyweight and waterproof copper-wire harness delivers all control signals, voltages and sensor feedbacks to the motors located in the mirrors, door locks and power windows. All components such as microcontrollers, switches and regulators are discrete and mounted on PCBs in separate modules. Figure 2 shows traditional door control architecture.

2. Automatic door locks, power windows and electrically controlled mirrors are integrated in a single control unit, which interfaces through a CAN interface with a central control unit.

The microcontroller is usually embedded into a PCB or hybrid and mounted inside the center of the car door. All control lines to switches, sensors and motors are done through traditional copper wires, which are protected against moisture, dust and water. To save cost and weight, semiconductor manufacturers started to incorporate more functions into the switch itself. The idea was to put as much intelligence into a single power switch, so that the switch itself could control its functions and also communicate with the rest of the car. A common combination consists of a power driver, microcontroller, voltage regulator and sensor interfaces. All these functions are usually integrated into a multi-chip package as silicon integration of low-voltage/high-speed microcontroller structures, and power/high-voltage processes would not allow meeting the cost target for such ICs. The control and communication with other units in the car take place through CANs or LINs. The new, highly integrated device is now encapsulated directly in the housing of the window, mirror or door-lock motor and does not require separate protection against the harsh automotive environment (Fig. 3 ).

3. Door control functions shown in Figure 2 are now integrated in a single package encapsulated directly in the housing of the window, mirror or door lock motor. It does not require separate protection against the harsh automotive environment.

The central in-door control with the heavyweight copper-wire harness disappeared and has been replaced with a single device controlled through a dual-wire differential CAN or single-wire LIN bus architecture. All this works great for the car manufacturer and the cost savings are obvious and significant, but this new architecture challenges traditional automotive power ATE architectures.

Conventional power automotive test architectures are not prepared to test such high-power ICs, as the test requirements for such devices are very diverse. Threshold measurements for comparator sensor inputs compound the testing problem when the testing is done in a multi-site environment, causing serialization of the tests that increases the overall cost of test. The fundamental problem with the newly integrated device is that the test engineer does not have direct access to control gates of the switches anymore. To switch the device in the desired state, the user has to download and execute the correct routine into the microcontroller of the IC. This challenges conventional power ATE architectures, as this level of synchronization between instruments is not available (Fig. 4 ).

4. Conventional ATE architectures are not well suited for automotive SoP testing because they don’t allow synchronization between instruments.

The IC mandates that all test instruments are completely synchronized to each other, so the microcontroller vector burst can start the control sequence for turning on one of the half-bridge drivers, and the DC instrument can trigger the measurement in a timely synchronized manner to capture the result. This requires strict synchronization across all test instruments. Therefore, it is mandatory that the ATE architecture support strict synchronization across the entire instrumentation suite, AC, DC and digital.

Teradyne's FLEX platform architecture is designed to ensure the highest throughput possible by approaching "device-limited" test time — testing limited only by the operational speed of the device under test (DUT). The key capability in the platform is the Sync-Link architecture that allows users to synchronize the setup and control of the test system instrumentation in "device clock time."

Using special instrument microcodes, users can set up and control AC and DC instrumentation with the digital pattern generator. This allows the user to control device activity and tester instrumentation through the digital pattern, which is operating at device clock time. The instrument microcodes can be programmed on a vector-by-vector basis within each time domain of the device, enabling faster instrument setup and test execution. The Sync-Link architecture provides synchronization and control of each system instrument in device clock time using the digital pattern for each device time domain. The architecture ensures that the tester generates precise test frequencies, and that each core of the device can have a full complement of instrumentation completely synchronized to its time domain.

A second key architectural enabler for achieving device-limited test time is the background digital signal processing (DSP) environment. The background DSP takes data movement and processing out of the test flow and puts it into the background (Fig. 5 ). Therefore, no test time overhead for test-data processing is added to the test program. The combination of the Sync-Link architecture and background DSP allows a user to directly replicate the DUT operating environment for functional system test at device-limited test speed.

5. In synchronized ATE, users control device activity and tester instrumentation through the digital pattern, which is operating at ‘device clock time.’

Automotive SoP devices represent a major trend in the market of automotive power semiconductors. Testing of such devices mandates that the ATE architecture support pattern-generator-controlled and fully synchronized digital, AC and DC instrumentation. This emerging requirement will overwhelm conventional power ATE architectures that use a pure computer-based serial instrumentation programming, causing increased cost of test for the conventional ATE architecture. An ATE architecture that allows instrument microcode control over all aspects of the digital, AC and DC instruments to occur simultaneously without the limitations of a serial computer bus will increase test coverage while reducing overall cost of test.