Laser-Induced Debug and Failure Analysis

New process technologies are creating unprecedented challenges for device analysis. Aggressive design styles and statistical process variation are producing performance yield problems that are no longer solely in the domain of the design or fabrication process. Even designs that have passed pre-silicon verification typically have lower-than-expected yield that cannot be found with traditional failure analysis (FA) techniques. Innovative techniques are required to pinpoint these complex design and process issues.

The use of a laser for injection of optical signals is a well-known technique in the field of failure analysis for purposes of fault isolation. Several techniques have been developed in this area, varying by the wavelength of light used and the method of signal extraction. Examples include optical beam-induced resistance change, laser-induced voltage alteration and optical beam-induced current.

More recently, similar techniques have been demonstrated for probing ICs operating normally on automated test equipment (ATE) for purposes of debug rather than FA. These techniques have been named soft defect localization (SDL) and laser-assisted device alteration (LADA). The two techniques are nearly identical, except for their laser wavelengths: 1.3 and 1.06 µm, respectively.

1. The effect of a 1.06 µm laser on the output of PMOS and NMOS transistors.

The effects observed on ICs depend on the wavelength of the laser selected. A 1.3 µm laser, whose photons are not sufficiently energetic to generate electron-hole pairs, locally heats the silicon or interconnect wiring. This typically causes a delay in the signal being probed. A 1.06 µm laser beam generates photocurrent caused by the interaction of generated electron-hole pairs with the p-n junctions in the silicon. This photocurrent acts as a current source in parallel with NMOS transistors, while it reduces the magnitude of the threshold voltage of PMOS transistors. This effect is shown in Figure 1. In a CMOS circuit, the effect on the PMOS typically dominates, advancing the rising edges of pulses and delaying the falling edges, as also shown in Figure 1 . For certain laser powers, up to 2 mA of photocurrent in n-diffusions can be induced. This is comparable to the approximate I_dsat value of 0.7 mA/µm found in many modern CMOS processes, so it is clearly possible to influence the behavior of transistors under these circumstances.

2. A schematic of a general application involving LADA and SDL techniques.

The general application of SDL and LADA is depicted in Figure 2 . The tester (ATE) is put into a continuous loop as in other forms of optical probing. The test parameters, such as temperature, voltage and frequency, are set very close to the border between passing and failing. A laser beam is scanned over the device under test (DUT) by means of a laser-scanning microscope (LSM). If the laser beam hits a critical circuit, the DUT may change from a passing to a failing state or vice-versa. Once per test loop, the ATE outputs the pass/fail signal. This signal is recorded along with the standard reflected-light signal at every (X, Y) pixel location.

For the following results, three types of LADA-related measurements were generated. A prototype of the Credence GlobalScan system operating at 1.06 µm was used to collect the data from a test chip called Azuma. First, timing shifts were observed in an inverter scan chain (Δt mapping). Next, changes to the frequency of ring oscillator circuits were observed (Δf mapping). Finally, a 1.06 µm laser was used to induce passing/failing behavior in a circuit with a controllable race condition.

To quantify induced timing changes, an inverter chain was probed. This structure consisted of 20 identical inverters (2.5/4.0 µm NMOS/PMOS) separated by 10 µm, and each had a separate n-well. The output of inverters #1 and #20 were connected to external pads located several hundred microns away from the chain.

A fast-pulse generator was connected to the input of the inverter chain, and the outputs from inverters #1 and #20 were connected to the start and stop inputs of a time-measurement unit, which recorded the difference in arrival times of the trailing edges of the two pulses to 1 psec resolution (Fig. 3 ). The 1.06 µm laser was then scanned over the inverter chain, and the changes in pulse arrival times (advance or delay) were recorded vs. the (X, Y) coordinates of the laser beam.

3. The experimental setup used to obtain the laser-induced timing-variation data.

4. The timing shifts and optical image of an inverter chain. Red = Delay. Blue = Advance.

Figure 4 shows the results of the scan delay time superimposed on the optical image. Figure 5 shows two cross-sections of this data along the inverter chain through the NMOS and PMOS transistors. The site of each inverter is labeled according to whether the edge of the pulse was rising or falling at the output of that inverter. At each inverter stage, probing the NMOS and PMOS produces opposite timing shifts, with the change in the PMOS being stronger. Also, the odd- and even-numbered inverters have opposite timing shifts. This is expected, as the timing edge (the trailing edge of the pulse in this experiment) alternates between rising and falling in adjacent inverters. The final stage exhibits a larger timing shift than the others. This is because it is loaded more heavily than the others. The change in delay from a stage Δt scales roughly as Δt = C node V_dd/ ΔI source, where C node is the capacitance on the node, V_dd is the power supply voltage and ΔI source is the change in the drive strength of the gate caused by the LADA effect.¹

5. Slices through NMOS and PMOS regions of an inverter chain showing opposite delay effects.

The 500 MHz ring oscillator structure of the Azuma device was used to characterize laser-induced frequency variations. The output of this ring oscillator is available through a divide-by-32 stage, which results in a 15.625 MHz signal at an output pin. The actual output was ~16 MHz because of variations in the device. Figure 6 shows a schematic of the experimental setup.

6. A schematic of the experimental setup used to obtain the laser-induced frequency map.

The goal of the experimental setup was to measure the frequency of the ring oscillator at every pixel as the laser scanned over the device. Once again, the Credence GlobalScan system was used to accomplish laser stimulation of the Azuma device. The 1.06 µm laser was used to obtain the frequency variation maps. The scan resolution was selected as 512 × 512 pixels.

The results from the experiments are shown in Figures 7 and 8 . The left-hand images show the reflected light image of the areas that include the ring oscillator structure at 20× and 100× magnifications, respectively. The effect of the 1.06 µm laser on the ring oscillator structure can be clearly seen in the dark areas of the right-hand images. The dark areas are indicative of lower frequency of the ring oscillator as a result of laser stimulation of the active inverter stages.

7. A 20× magnification LSM reflected image (left) shows the four ring oscillators of the Azuma device. The 500 MHz ring oscillator is the top-most structure. The frequency variation map (right) of the ring oscillator structure is shown under the influence of the 1.06 µm laser.

8. A 100× magnification LSM reflected image (left) shows the four ring oscillators of the Azuma device. The 500 MHz ring oscillator is the top-most structure, with the left-most 37 stages active. The frequency variation map (right) of the ring oscillator structure is shown under the influence of the 1.06 µm laser.

When the laser stimulates an inverter structure, the PMOS transistor is dominantly affected in the following way: The low-to-high transition times decrease and the high-to-low transition times increase. Furthermore, the change in the high-to-low transition times is greater than the change in the low-to-high transition times. This mismatch results in a lower output frequency when the laser stimulates the inverter structure.

To demonstrate the LADA effect in a realistic debug situation, a race condition was simulated on a test chip in which a data value arrives late to a scan latch. The chip contained a 10-bit counter that was driven by an externally generated 100 MHz clock. After a pre-determined number of clock cycles, the data value in the counter was captured by a set of scan latches. The timing for the capture was determined by a pulse that had a user-controllable delay, with respect to the 100 MHz clock. The setup is sketched in Figure 9 .

9. A schematic of the experimental setup used to obtain the pass/fail mapping.

After the data was captured, it was shifted out of the latches and compared against the pre-determined value. A discrepancy between the pre-determined value vs. the scanned data generated a "fail" signal on an external pin. If the data values matched, a "pass" signal was generated. The pass/fail signal was then recorded by the prototype GlobalScan system, along with the (X, Y) pixel data.

10. The optical image and location of a critical failing circuit in an induced race condition. Also shown are bit-flips in nearby scan latches.

The variable delay on the latch pulse was set so that the part was on the border between passing and failing. The border region was about 40 psec wide. The laser was then scanned over the sample. The resulting pass/fail map is superimposed over the optical image in Figure 10 . The scan took ~10 minutes to complete. There is a clear spot, marked by an arrow, which shows a sensitive circuit that was identified by the system. Also of interest are the two strong spots nearby that show how the laser can flip bits in the scan-latch circuits themselves. These "false failures" are an artifact of LADA, and show that some care is required in interpreting the data. In this case, it was obvious that these were not the critical circuits, because the bit-flipping persisted even when the DUT was biased far from the failing condition.

The effect of a 1.06 µm laser beam (the LADA effect) on operating CMOS circuits can be used to isolate sensitive circuits and design marginalities of IC devices. Using a prototype GlobalScan system, which included an advanced LSM and full CAD navigation capabilities, timing shifts and frequency shifts of test circuits were measured. The utility of LADA for rapidly isolating a realistic race condition in a circuit containing scan latches was demonstrated. LADA is expected to become an increasingly important tool for debug and failure analysis in LSI circuits.