Four New Yield Models for Deep-Submicron Designs

Laura Peters, Senior Editor -- Semiconductor International, 11/1/2000

Below 0.5 µm feature sizes, engineers require more accurate models to forecast yields, speed yield ramping and evaluate a product's manufacturability. The most popular models used today to estimate yield loss are area-based models, including the Poisson, critical area and negative binomial models. Unfortunately, these yield estimations do not always provide the needed accuracy for deep-submicron devices, according to Yanwen Fei and Wojciech Maly of Carnegie Mellon University (Pittsburgh), and Paul Simon of Philips Semiconductors (Nijmegen, Netherlands).

Alternatively, the group proposes four new models that consider such design attributes as feature size, number of transistors, design density and the number of metal layers. Testing the performance of eight models across 23 digital CMOS ICs and over 40,000 wafers, the researchers determined the feature size model and the comprehensive model (Table) most closely matched actual yields with a maximum error of 3.5%, relative to almost 15% using the Poisson model.

Yield modeling is especially challenging in cases where a layout is not yet available to estimate critical area across the chip. Instead, Fei, Simon and Maly use design density (Dd), feature size (Fs) and number of interconnect layers (Lm), each with power factor fitting parameters r, p and k. The comprehensive model is defined as

Y = e-K where K is:

P x Ntr x Ddr x Fsp x Lmk

In this formula, P is the possibility of failure and Ntr is the number of transistors. The feature size model is identical to the comprehensive model without the fifth term.

The researchers adopted a strategy that minimized impact on yield other than that caused by random defects. They processed all 40,000 wafers on the same manufacturing line. They tracked yield data over three periods of time in a 300-day period, limiting the time interval of observation to ensure model parameters were stable. The group categorized the sample sizes as small (100-500 wafers), medium (501-1000 wafers) and large(>1000 wafers) and collected data from devices covering a range of die sizes, minimum feature sizes (0.5, 0.4, 0.35 or 0.25 µm), and metal levels (3 or 5). For each 100-day period, they used median wafer yield values, rather than mean, because most yield data does not follow a Gaussian distribution. Yield values were computed for each 100-day time zone.

The researchers then fit the data separately for the three time zones and tuned the model parameters to minimize average error, R². Maximum error for the Poisson model and critical area model were 15% and 12%. The simple model 1, simple model 2 and design density estimations predicted yield with better accuracy, with maximum error of 7%, 11%, 8% and 7%, respectively. The feature size and comprehensive models gave the most accurate yield values with a 3.5% maximum error and R² = 0.990 in both cases.

The researchers from Carnegie Mellon and Philips will present full results using all models at next month's IEEE IEDM (International Electron Devices Meeting) in San Francisco. They will show how the four new models provide more accurate representations of yield at sub-0.5 µm feature sizes than area-based models. Most importantly, engineers using the new models can accurately forecast yields before the design process is completed and in plenty of time to shape manufacturing and processing decisions.

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