A Preview of Next-Generation CMOS Designs

Peter Singer, Editor-in-Chief -- Semiconductor International, 11/1/2000

Researchers from Fujitsu and Sony are scheduled to present a 110 nm CMOS technology with copper and very low-k (VLK) interconnects, designed for high-performance system-on-a-chip cores. The group used a hybrid approach for implementing the low-k material, using VLK dielectric (Dow's SiLK) at the trench level and USG (undoped silicate glass) at the via level. Copper interconnects were formed using a dual hard mask structure made of SiN/SiO₂. The aggressive dimensions were patterned using KrF 248 nm lithography and optical enhancement techniques, including phase shift mask and optical proximity correction (OPC).

Taiwan Semiconductor Manufacturing Co. (TSMC) will unveil a 130 nm CMOS technology using 193 nm technology (with OPC) and copper/low-k interconnect. Thermally grown gate oxides with no anneal were employed for high-performance core and I/O devices. This was followed by polysilicon deposition and DUV gate patterning. The researchers note that gate line-edge roughness (LER) can have a significant impact on off-state leak current for deep submicron MOSFETs. FSG is used for low-cost ASICs, while two unnamed low-k materials were investigated for high-performance applications.

Intel will take the wraps off a 130 nm technology featuring 70 nm transistors and six layers of copper interconnects with FSG (k=3.6) interlevel dielectric. Process highlights include shallow trench isolation, retrograde wells, shallow abrupt extensions, halo implants, deep source/drains and cobalt salicidation. The result is n- and p-channel low threshold voltage devices with 15% higher saturation drive currents and 10 times higher off-state leakage. "Highly manufacturable" gate oxides are 2.4 nm thick.