Dedicated Pre-Clean Reduces Epi's Thermal Budget
Arkadii V. Samoilov, Dale Du Bois, Paul B. Comita, David Carlson Applied Materials Inc., Santa Clara, Calif. -- Semiconductor International, 11/1/2000
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At a Glance | | |
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However, many of these devices are highly sensitive to thermal budget, in part because their dopant profiles must be as precise as possible, with minimal time-at-temperature that might cause diffusion. These applications increasingly require low-temperature epitaxy, where the process temperature is reduced from the traditional 1000-1200°C range down to the 600-800°C range.
One application that requires lowering the thermal budget involves a Bi-CMOS process in which the epitaxial layers of the bipolar transistors are grown after the MOS transistors have already been fabricated. The bipolar processes must not damage structures fabricated on the wafer under the epi layer, such as impacting the insulation layers and abruptness of the dopant profiles of the MOS transistor. Deposition of the base of the bipolar transistor often involves SiGe epi, a material in increasingly common use that is capable of expanding silicon technologies into the 100 GHz range.1
Another emerging epitaxial application that requires low thermal budget is elevated source/drain engineering of CMOS devices. Selective epitaxial growth of elevated source and drain is a potential solution for ultra-shallow junction formation.2
Much of the thermal budget in epi processing is due to the high-temperature cleaning step performed in the epi chamber before deposition. A new technique for lowering thermal budget, while increasing throughput and productivity, is to use a separate, reduced-temperature wafer-cleaning module that can service multiple single-wafer epi deposition chambers. This article describes the technology of such a cleaning chamber and its results on the epi process.
Traditionally, wafer cleaning has been performed for a period of time within the epi chamber prior to film deposition to remove native oxide. The conventional method of removing oxide is to bake the wafer in hydrogen gas at >1000°C immediately before deposition.
This method presents a problem with wafers already containing active devices. Users have also lowered the baking temperature by first performing a wet clean in a water-based solution of hydrofluoric (HF) acid, then baking the wafers at 900°C for 1 min in the epi chamber before deposition.
Attempts to further lower the temperature of the hydrogen bake inside the deposition chamber significantly slow down the pre-epitaxial cleaning process. Also, the deposition chamber may have residues that can outgas. Outgassing impedes native oxide desorption that requires as low partial pressures of oxygen and moisture as possible.3 Burdening the deposition chamber with the slow pre-epitaxial cleaning process also significantly reduces throughput.
| 1. A schematic of a multi-chamber cluster tool (Epi Centura) optimized system for low-temperature deposition. |
Second, eliminating the time spent cleaning the wafer from the overall epi process can significantly improve system throughput and productivity of low-temperature Si and SiGe films. One dedicated cleaning chamber occupies an unused port on the system, thus taking up no additional system footprint, yet it can service up to three epi deposition chambers.
Native oxide characterization
When pre-clean process is performed in a separate chamber, it is very important to ensure that moisture and oxygen partial pressures in the transfer chamber are reduced to low levels so that the transfer process itself does not result in wafer contamination. To verify the cleanliness of the transfer chamber, we first transferred a wafer to a deposition chamber where it was baked at 1100°C, followed by a Si layer deposited at 950°C. This procedure is known to produce an atomically clean surface.
Second, the wafer was moved to the transfer chamber for 15 sec. Then, the wafer was transferred back to the deposition chamber where a low-temperature capping layer was deposited at 680°C.
| 2. SIMS profile for a P-blanket wafer that was processed at a deposition chamber (950°C deposition), transferred to the transfer chamber for 15 sec, and moved back to the deposition chamber for a 680°C epitaxial deposition. The absence of an interfacial peak proves cleanliness of the transfer process. |
Before cleaning, the wafers need to be pre-processed in HF for the low-temperature bake to be effective. Treatment in a water solution of HF typically reduces the thickness of native oxide from several nanometers to a thickness of the order of one monolayer.
Figure 3 (left panel) shows SIMS data for a wafer that was dipped in HF, transferred to the deposition chamber and capped there with a silicon layer. No pre-epitaxial bake was performed on this wafer. The interface between the substrate and the cap had a high concentration of oxygen, carbon, chlorine, nitrogen and fluorine. Integrating the oxygen peak results in an oxygen surface concentration that corresponds approximately to a monolayer of oxide. Epitaxial deposition is impossible without removing this remaining oxide layer.
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| Click for full-size image 3. SIMS profiles. Left panel: A P- blanket wafer was HF-dipped and capped with a 680°C silicon epitaxial layer in a deposition chamber. Right panel: A P- blanket wafer was HF-dipped, baked in the cleaning chamber for 35 sec at 760°C and 20 sec at 795°C, an d capped with a 680°C silicon epitaxial layer in a deposition chamber. Inset: Schematic representation of oxide removal during the two-step cleaning process. |
Cleaning method
In the cleaning chamber we developed a two-step hydrogen bake sequence. The temperature of the first step is typically 750-770°C; the temperature of the second step is raised to about 770-795°C.
During the first step, the surface concentration of oxygen and carbon is decreased by about two orders of magnitude, as shown in the top inset of Figure 3 (right panel). The second step reduces contaminant concentration to below SIMS detection levels.
In the case depicted in Figure 3 (right panel), the wafer was baked for 35 sec at 760°C and for 20 sec at 795°C. After cleaning, the wafer was transferred to a deposition chamber, where an epitaxial silicon cap was grown at 680°C. SIMS analysis did not reveal any residual oxygen, carbon, fluorine or chlorine at the interface between the substrate and the epitaxial layer.
If a longer bake time is allowed, the temperature of the bake can be decreased even further. For instance, a process with 60 sec at 760°C and 60 sec at 780°C gives results that are comparable to those in Figure 3.
Therefore, the cleaning chamber allows flexibility in choosing process parameters, depending on thermal budget and throughput requirements.
| 4. AFM scans on 2 × 2 µm areas before (left) and after the treatment in the cleaning chamber. |
It can easily be seen that baking the wafer in the cleaning chamber resulted in roughness improving from 1.4 to 0.75 Å.
Additional surface data was obtained using high-resolution total reflection X-ray fluorescence (TXRF), an inspection method that probes surface metal concentration.
As summarized in Table 1, no metal adders, within 4×10 atoms/cm2, were observed.
| Table 1. High-Resolution TXRF Data for Wafers Before and After Treatment in the Dedicated Cleaning Chamber | |||||||||
| Surface metal concentration is given in 1010 atoms/cm2 | |||||||||
| K | Ca | Ti | Cr | Fe | Co | Ni | Cu | Zn | |
| HF-dip | <0.3 | <0.2 | <0.04 | <0.04 | <0.02 | <0.01 | <0.01 | <0.01 | <0.3 |
| HF-dip + dedicated clean | <0.3 | <0.2 | <0.04 | <0.04 | 0.04 | <0.01 | <0.01 | 0.03 | <0.3 |
Table 2 presents results of throughput analysis due to the use of a dedicated cleaning chamber. The first row shows the throughput improvement found using the dedicated cleaning chamber instead of the former process that involves a 60 sec bake at 900°C in the deposition chamber, 90 sec deposition, and a chamber clean for a system with up to three deposition chambers. A much longer bake may be required if one attempts to perform pre-clean at temperatures below 800°C inside a deposition chamber. The second row of Table 2 shows significant throughput gains using the cleaning chamber to replace a process with a 300 sec bake in the deposition chamber, 90 sec deposition, and a chamber clean. The throughput improvement (18%-74% for systems with one or two deposition chambers) derives from eliminating the bake step inside deposition chambers.
| Table 2. Throughput Benefits From Using a Dedicated Cleaning Chamber | |||
| 1 deposition chamber | 2 deposition chambers | 3 deposition chambers | |
| Replacing 60 sec bake in deposition chamber by dedicated cleaning chamber | 18% | 18% | 7% |
| Replacing 300 sec bake in deposition chamber by dedicated cleaning chamber | 74% | 74% | 57% |
Summary
Use of a dedicated chamber to perform pre-epi deposition cleaning allows native oxide removal with a low thermal budget, and significantly improves throughput of low-temperature Si and SiGe applications.
Wafers processed in the cleaning chamber showed no detectable contaminants, and the cleaned surface was actually significantly smoother because of cleaning down to a sub-angstrom level. •
Arkadii Samoilov, Ph.D., is a program manager of the silicon epitaxy technology development laboratory in the Epi Substrate Division of Applied Materials. Prior to joining Applied Materials in 1998, Samoilov was a Robert A. Millikan Senior Research Fellow at the California Institute of Technology (Pasadena), where he focused on research in semiconductor physics, superconductivity, ferromagnetism and ion implantation. He has 40 technical publications.Dale R. Du Bois is a senior member of the technical staff at Applied Materials. He has worked in the semiconductor capital equipment industry since 1976. Prior to this, he worked for Science Applications International Corp. (SAIC, San Diego) on various research projects for the Department of Energy and Department of Defense. He has received an A.S. Engineering degree from West Valley College (Saratoga, Calif.) and a B.S.M.E. degree from Santa Clara University (Calif.).
Paul B. Comita , Ph.D., is the director of technology in the Epi Substrate Division of Applied Materials. Prior to joining Applied Materials in January 1996, he was a member of the research staff at IBM Almaden Research Center (San Jose). At Almaden, he was employed in the area of chemical vapor deposition, etching and related semiconductor, flat panel display, and phase shifting mask technologies, although he was primarily focused on advanced technology for metal deposition. He has nine U.S. patents issued, and more than 45 technical publications in the area of microelectronics technology. He received his doctoral degree at the University of California, Berkeley, and did post-graduate research at Stanford University (Stanford, Calif.).
David Carlson is a senior member of the technical staff at Applied Materials. He has been employed with Applied Materials for more than 22 years and has been involved in epitaxy for 30 years.
REFERENCES
- For a review, see F. Schaffler. "High-mobility Si and Ge structures", Semicond. Sci. Technol. 12, 1515
(1997).
- K. Miyano, I. Mizushima, and Y. Tsunashima, Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials, Sendai, 2000, p. 400.
- G. Ghidini and F. W. Smith. "Interaction of H2O with Si(111) and (100)", J.Electrochem. Soc. 131, 2924 (1984).
The authors would like to acknowledge P. Pianetta of Stanford University (Palo Alto, Calif.) for performing high-resolution TXRF analysis.
