SiGe Fuels High-Speed Communications

David C. Ahlgren, Basanth Jagannathan, IBM, Hopewell Junction, N.Y. Stephen St. Onge, Mark D. Dupuis, IBM, Essex Junction, Vt. -- Semiconductor International, 11/1/2000

Like many gallium arsenide devices, the Si/SiGe heterojunction bipolar transistor (HBT) can also address several high-speed wireless and wired needs by effectively mimicking the bandgap-engineered attributes of compound semiconductors in a silicon device. Work in this area, led primarily through research activities at IBM's Watson Research Center in Yorktown Heights, N.Y., has launched a revolution in the semiconductor industry. Starting with a 200 mm silicon wafer, we can integrate unprecedented levels of functionality by combining SiGe analog and rf circuits with CMOS logic components for state-of-the-art BiCMOS production (Fig. 1). Currently producing a wide variety of high-speed analog chips and meeting stringent circuit specifications for a range of wireless protocols, SiGe technology is combining active and passive elements, and logic and analog functions in ways never before possible. SiGe also takes advantage of the economies of scale made possible by large silicon manufacturing volumes, low defect densities and CMOS process maturity.

The Si/SiGe HBT

We make the transition from a silicon-only homojunction to SiGe HBT by growing an epitaxial (epi) layer of germanium-doped silicon on the silicon substrate. Basic physics tells us that the atomic size difference between these two species necessarily results in a lattice mismatch, which must be managed in integrating this layer. While a certain level of strain is required for bandgap reduction and, in fact, drives HBT performance, we must control strain to prevent lattice defects. This limitation has been extensively studied and Matthews and Blakeslee curves¹ relate film thickness to strain in a Si/SiGe system.

An equally important consequence of this grown SiGe epi layer is to simultaneously form a narrow, boron-doped base region of the NPN transistor, replacing the conventionally ion-implanted base in bipolar junction transistors (BJTs). The epi method frees device designers from the confines of Gaussian profiles and implant channeling effects and results in improved reliability compared with the silicon double poly BJTs and GaAs HBTs.² We engineer the HBT bandgap (Fig. 2) to dramatically improve silicon device performance.³ Performance improves because we are reducing the energy barrier to electron injection in the base region of the HBT, improving device current gain, while also forming a drift field that accelerates electrons across the base, increasing f_T, a measure of HBT speed.

Growing SiGe epi layers

Development of a manufacturable SiGe epi process was the fundamental breakthrough that enabled the SiGe technology revolution. IBM developed a UHV-CVD process (with hydrogen-passivated pre-clean) that enabled an in situ boron-doped SiGe epi base.⁴ The low-temperature epi (LTE) (500°C) process enables defect-free SiGe growth and simplifies process integration. Conventional blanket epi techniques were not suitable for this task because they use high temperatures for growth and pre-clean. The LTE method also helps precisely control the boron base width and doping profile necessary for HBT devices.⁵ Dislocations in the silicon crystal - which cause emitter-to-base, collector-to-base and/or collector-to-emitter leakage - typically limit the device yield of silicon bipolar devices. One might expect the SiGe HBTs to have a higher probability of dislocations because of the strain in the SiGe layer and possible defects from the epi process. However, by adopting sound epitaxial growth techniques and optimizing the SiGe strained layer characteristics, we were able to minimize strain-induced defects. The LTE process produces a relatively defect-free epi layer and does not contribute to yield loss. IBM has produced arrays of 4000 transistors, used as line monitors, with >90% yield in high-volume manufacturing. The company has demonstrated similar yields on SiGe devices with 30,000 HBTs and more than 1 million FETs.

Using the UHV-CVD LTE method, IBM qualified the earliest SiGe commercial process in 1996. This technology revolved around an HBT with a maximum available power gain (f_MAX) of 65 GHz⁶ (Fig. 3) and various active and passive device support elements, giving circuit designers a wide palate to realizing high-performance analog circuits.

3. Cross-sectional SEM of a SiGe heterojunction bipolar transistor.

Since IBM's foray into the SiGe field, several other epitaxial methods have been proposed, including molecular beam epitaxy (MBE), low-pressure CVD, rapid thermal CVD and, most recently, low-energy plasma-enhanced CVD. Though systems are commercially available, little data has been published demonstrating tool performance or commercial device characteristics.

The SiGe fab

With the addition of the LTE process and UHV-CVD tooling, one can convert an existing silicon CMOS fab to one that can produce SiGe BiCMOS products.

The sharing of common processes and line controls with the CMOS technologies capitalizes on process development and yield learning of the high-volume CMOS fab. In addition, we were able to create a SiGe BiCMOS technology with FET characteristics equivalent to an existing CMOS technology, so that designers could use existing ASIC logic libraries and design methodologies for the SiGe BiCMOS technology. Merging large CMOS digital logic function with high-performance HBTs paves the way for high levels of integration not possible using GaAs.

The integration method is key to ensuring that the addition of the SiGe HBT to the CMOS process does not affect FET device characteristics. Similarly, CMOS processing steps should minimally affect bipolar device performance. Primary considerations are thermal budget and the trade-off between process modularity and process sharing.

In IBM's 0.5 µm SiGe BiCMOS technologies^6-9 we used a "base = gate" integration method. With this approach, we use a common layer stack for both the NPN SiGe epi base and the FET polysilicon gates, and reduce the total number of process steps.

4. Compared with the base-equal-gate integration scheme, the base-after-gate alternative avoids any dopant redistribution in the critical HBT base region due to the high-temperature S/D anneal and oxidation in typical CMOS processing.

However, changes in thermal cycles with subsequent CMOS generations create difficulties. For instance, CMOS technology includes high-temperature source/drain dopant activation and gate sidewall oxidation. To maintain a high-performance narrow-base HBT, one must limit and control the base's exposure to heat. To overcome this incompatibility, IBM developed a base-after-gate integration scheme (Fig. 4) for its 0.24 µm SiGe BiCMOS technology.¹⁰ Here, the HBT is built after the FET anneals, minimizing thermal cycling of the SiGe base. Since HBT processing is at low temperature, thermal effect on the FETs is minimal. Also, the modularity of the base-after-gate approach simplifies migration of the HBT to future-generation CMOS technologies and the creation of derivative technologies.

The SiGe BiCMOS market

5. A SiGe HBT can operate at maximum oscillation frequencies of 65 GHz. But by reducing operating currents, one can trade excess speed for reduced power consumption.

Some of the early payoff in using the Si/SiGe HBT was its ability to perform at very high speeds: 65 GHz maximum oscillation frequency, f_MAX. Because these high device switching speeds are not necessary for most wireless circuits operating at 900 MHz and 2.4 GHz, the SiGe leverage comes from being able to trade the excess speed for improvement in other device attributes; most notably, low-power operation (Fig. 5).

The SiGe HBT has also demonstrated the ability to provide excellent high-performance characteristics with very low noise, at high power gain, and with great linearity; allowing designers wide latitude in solving specific circuit requirements. Additionally, owing to SiGe's proven ability to achieve power-added efficiencies reaching 70%,¹¹ SiGe has spawned a rich area of design activity for power amplification.

Another essential for analog circuitry is high-quality passive elements. IBM's SiGe technology has provided technical leadership in the development and integration of benchmark passives including high-Q inductors¹² and MIM (metal-insulator-metal) capacitors.¹³ The superlative performance margin achieved from this combination of active and passive devices has positioned SiGe technology to meet stringent specifications for circuits used in a wide range of wireless protocols: AMPS (U.S. analog), PCS (digital), PDC (Japan), GSM (European standard) and CDMA (Code Division Multiple Access).

Perhaps the biggest leverage for SiGe in the marketplace is its ability to be integrated with CMOS, providing unsurpassed value as a BiCMOS technology. Compatibility with ASIC design methodologies is essential to the effective combination of high-performance attributes of the HBT in analog function and CMOS's very large digital designs, which we have demonstrated,¹⁴ and is essential to all IBM BiCMOS technologies. As SiGe design experience grows, further integration of circuit elements becomes possible. We expect system-on-a-chip levels of integration within the next few years.

SiGe BiCMOS technology also provides design flexibility. At the device level, one can exploit the raw speed of the intrinsic SiGe HBT to design at frequencies above 5 GHz, speeds unattainable by other silicon technologies. At the circuit level, one can explore the trade-off between gain and bandwidth to achieve whatever figure of merit is of interest (for example, low power, high linearity, low noise or high dynamic range). At the system level, the designer can exploit the rich feature set of SiGe BiCMOS to redesign systems from the top down.

6. A high-speed PRML-read channel chip built on a 0.25 µm BiCMOS process demonstrates the integration levels possible with SiGe technology.

Design flexibility is manifest in the wide range of applications that use SiGe BiCMOS analog/rf devices, including home microelectronic rf products such as low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers and transceivers. High-performance analog designs include ADCs, DACs, frequency synthesizers and intermediate-frequency (IF) filters. Other product design activities focus on SiGe power amplifiers. Additionally, IBM has announced a GPS receiver featuring the first use of a SiGe front end using a powerful direct-conversion rf architecture. Customers are also using SiGe BiCMOS for storage applications including high-speed partial- response maximum-likelihood (PRML) read channels using IBM's 0.25 µm BiCMOS (Fig. 6), designed for use in hard drives. In addition, the same process techniques that allow SiGe BiCMOS use in power amplifiers is being applied to state-of-the-art magneto-resistive preamplifiers for hard drives.

Progress has been extremely rapid in the introduction of customer-designed products across a broad range of commercial and consumer markets, creating products such as a 10 Gb/s SONET, 1-2.5 Gb/s Ethernet, cellular base station and handset components, optical transmit/receiver systems, wireless LAN and digital network switching.

In addition to demonstrating the ability to match worldwide specifications for current cellular protocols and new standards for wide-band CDMA (WCDMA), IBM SiGe promises to be a major factor in emerging standards for home wireless products: Bluetooth and IEEE 802.11.

Future directions

IBM is now in volume production of its third-generation SiGe technology, and is in the process of moving 0.18 µm SiGe technology from development to its Burlington, Vt., manufacturing facility.^15,16 Experience gained from the past years of production will speed the development of next-generation SiGe technologies to meet the design community's ever-growing appetite for higher performance and integration.

Future SiGe technology offerings are expected to include enhancements to the FETs and the HBT, and the addition and refinement of active and passive components. The broad range of applications, each application with its own unique requirements, may demand multiple versions of each technology generation. Modular integration approaches, such as the base-after-gate approach, can simplify development of these derivative technologies.

FET enhancements will be adopted from future-generation CMOS technologies. Generational CMOS changes in processes and thermal cycling constraints will be considered when integrating the CMOS and HBT processes. The base-after-gate method simplifies integration due to its modularity and isolation of the HBT from CMOS thermal cycles.

IBM plans to improve this powerful core technology through vertical and horizontal scaling and modification of the HBT structure. Horizontal scaling results from improved photolithography tooling and processes. Shrinking the HBT requires a corresponding shrink of the interconnect wires feeding the device, while the migration to copper interconnects helps alleviate the electromigration issue relating to the shrinking of these wires.

Vertical scaling will involve modifications to the LTE process as well as minimizing the subsequent diffusion of the base and collector dopants. A modular integration approach, such as base-after-gate, helps reduce this diffusion. Recent advances in rapid thermal processing will also prove beneficial in reducing overall thermal budget. Further improvements in f_MAX will require modifications of the device structure to keep reducing device resistances and capacitances.

Higher product integration levels are driving a strong demand for high-quality on-chip passive components. The impressive suite of passive components available today can be enhanced through the use of low-k dielectrics to reduce parasitic capacitance of inductors, capacitors and resistors, and high-k dielectrics to increase capacitance per unit area of MIM, MOS, and polysilicon capacitors.

Thicker and lower-resistivity metals can be used to improve inductor quality. We may integrate SiGe devices with SOI substrates or MEMS devices in future technology generations as product demands require.

Summary

Within a relatively short span of time, SiGe BiCMOS technology has moved from an R&D curiosity to volume production. SiGe BiCMOS technology can match the performance of III-V semiconductors and features the integration and manufacturability capabilities of silicon processing.

The HBT is produced using low-temperature epitaxy to grow a high-yielding SiGe base layer with in situ boron doping. Integrated with standard ASIC CMOS logic, the SiGe BiCMOS process can be manufactured in a standard silicon CMOS fab. The combined performance and integration capability is being exploited to produce a broad range of products for wired and wireless communications, computer disk drive and high-speed test applications. For more information, see www.chips.ibm.com/bluelogic/showcase/sige/ .

David C. Ahlgren is senior engineering manager of SiGe BiCMOS development with IBM's Communications Research and Development Center in Hopewell Junction, N.Y. Previously, he has held numerous positions at IBM in SiGe technology development and silicon bipolar process integration, qualification and production. He has a B.A. from DePauw University (Greencastle, Ind.) and a Ph.D. in chemical physics from the University of Michigan (Ann Arbor). e-mail: ahlgren@us.ibm.com

Stephen St. Onge is the manager of mixed-signal technology development at IBM's semiconductor facility in Essex Junction, Vt. Since joining IBM, he has been involved in the development of bipolar, BiCMOS and SiGe BiCMOS technologies. He has an A.S. in electrical engineering technology from Vermont Technical College (Randolph Center) and a B.S. in electrical engineering from the University of Vermont (Burlington).

Mark D. Dupuis is working in process integration for SiGe BiCMOS technologies at the IBM facility in Essex Junction, Vt. He was formerly a process engineer for silicon and dielectric LPCVD films. He has a B.S. in engineering physics from the University of Maine (Orono) and an M.S. in materials science from Syracuse University (Syracuse, N.Y.).

Basanth Jagannathan joined IBM three years ago and is working on SiGe epitaxy and technology integration issues. He has a Ph.D. in electrical engineering from the State University of New York at Buffalo.

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