Following a Steep Learning Curve for Copper
-- Semiconductor International, 10/1/2000
As leading-edge device manufacturers rush to integrate copper interconnects with oxide and low-k dielectrics, they must simultaneously devote considerable resources to advanced copper deposition methods for the coming 100 nm device generation. To fill sub-0.25 µm vias of increasing aspect ratio (AR), the logical transition from copper PVD to ionized PVD to CVD seems likely, though alternative techniques that may include copper doping or pulse electroplating are being explored. No matter which alternative is chosen, companies are following a steep learning curve in copper deposition, as evidenced by the variety of papers presented at IEEE's International Interconnect Technology Conference (IITC) in San Francisco this year.Exploring the Alternatives
Engineers from Motorola's Advanced Products Research and Development Lab (Austin, Texas) found they could improve the adhesion of copper to silicon nitride and oxide by incorporating a small amount of magnesium into the copper. Their studies of CuMg/Cu/ CuMg stacks showed magnesium diffuses through the copper and aggregates at the surface upon annealing. The surface magnesium reacts to form self-limiting oxide and fluoride films that hinder copper oxidation. Motorola's extensive electromigration tests showed no difference in median time to failure or distribution width for CuMg alloy relative to pure copper.
Pulse Plating
Among electrochemical deposition methods, the expected advantages to pulse plating over DC plating include void-free filling and greater tolerance to the morphology of the copper seed layer. Already proven in PCB applications, pulse plating combines a low forward current with a high current at the anode to increase the throwing power of copper into high AR features. Downsides have included negative effects on reflectivity, sheet resistance, film density, electrical yield, via chain resistance and electromigration. There also are concerns about incorporation of contaminants, such as oxygen, carbon, chlorine, sulfur and fluorine (from plating additives) into the deposited film. At IITC, researchers from Applied Materials (Santa Clara, Calif.) demonstrated that copper films deposited by pulse plating can provide void-free filling of 0.2 µm x 1.1 µm features with controlled over-plating, no change in film density (by RBS), no change in contaminant distribution (by SIMS) and a tight distribution of Kelvin via resistance. In addition, via chain yields of 110k 0.22 µm and 170k 0.28 µm chains compared favorably to those of DC plating.
TSMC (Hsinchu, Taiwan) conducted studies to determine the film properties and gap fill behaviors of the DC and pulse plating. They determined that the copper self-annealing process is slower and the reflectivity smaller for the pulse-processed films, which correlates with larger grain size. Grain size in pulse plating is also independent of plating current, unlike in DC plating where grain size decreases with increasing current. Pulse plating tends to increase the rate of deposition in the trench relative to field areas, even after the trench is filled. This "memory effect" was thought to result from having a deficient amount of suppressor in the trench. This also may explain the higher deposition rate in densely patterned areas. The TSMC researchers propose the gap filling mechanism in DC plating is mainly controlled by the additive diffusion, whereas the rate of additive adsorption controls filling in the pulse process.
CVD, Extending PVD
Ionized PVD approaches are now being adopted widely for both TaN barrier deposition and copper seed deposition. Taking this process one step further, engineers from Toshiba (Yokohama, Japan) found that by placing an ion reflector between the plasma and wafer, a small modification of a long-throw sputtering tool, the system can better control ion flux to the wafer and improve across-the-wafer deposition uniformity. In this configuration, a substrate bias promotes transportation of copper ions to the bottom of vias. Via holes 0.2 x 0.2 µm in size with an AR of 4 were then filled by electroplating. Toshiba also demonstrated conformal TaN deposition in 0.17 µm features with an AR of 5.
Researchers from Samsung (Kyounggi-Do, Korea) studied a process combining ionized PVD seed layer deposition with copper CVD fill of 2 x 2 µm features with an AR of 5. They determined that an ionized PVD film only 40 Å thick provides good adhesion between the TaN and CVD copper film, low via contact resistance and the needed (111) grain texture. Samsung used a blend of (hfac)Cu(tmvs) with extra tmvs and a chemical additive to increase deposition rate (to 1000 Å/min). Step coverage was >90%, and film resistivity (1.8 µW-cm) was comparable to the copper PVD film of the same thickness.
-Laura Peters
