Across the SEA, A Focus on Strategic Partnerships
Jeff Bruchez, Director of Dissemination, SEA -- Semiconductor International, 10/1/2000
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At a Glance | | |
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The Semiconductor Equipment Assessment initiative (SEA) - a European Community-funded initiative - continues to adopt the strategy it put in place in 1996, which offers European equipment and material suppliers a flexible path to develop their product innovations through to fully productive solutions.
A high level of success has been achieved within SEA projects to date with significant improvements in performance, equipment reliability, productivity and improved user satisfaction. Indeed, a recent survey by VLSI Research (San Jose, Calif.), stated "European suppliers of semiconductor equipment have made impressive gains in customer satisfaction during the past year." There are nine citations for European Community-based equipment companies that are rated within the top 10 in their relevant categories. Seven of these companies (Karl Suss, 2 categories; SEZ; Steag Electronic Systems; ASML; Schlumberger; ICOS Vision Systems) have had their equipment assessments completed in a total of 13 SEA projects.
SEA projects are user-driven assessments and have attracted a high degree of worldwide participation. Table 1 lists the component manufacturing companies in SEA and the number of projects in which each is involved. There are now, in fact, more non-European partners than European ones, showing the international nature of SEA. The participation level of leading European companies in SEA is very high. The organizations I300I, Selete and MEDEA also have been involved directly or via their IC partner companies.
| Table 1. SEA Participants (No. of Projects) IC, Microsystem and Sub-System Manufacturers | ||
| USA | ||
| AMD (5) | Intel (2) | National Semiconductor (2) |
| Analog Devices | Lucent (3) | PerkinElmer Optoelectronics |
| Cypress (2) | Micron | Texas Instruments (6) |
| IBM (3) | Motorola (4) | Xerox PARC |
| ASIA | ||
| Anam Industrial Co. (2) | Hyundai | TSMC |
| LG Semicon | Samsung | |
| EUROPE | ||
| Alcatel Microelectronics (6) | GPS (Mitel) (2) | SMST (2) |
| Austria Mikro Systeme (2) | Infineon/Siemens (17) | STMicroelectronics (19) |
| Celestica | Philips Semiconductors (9) | Temic (Atmel) (5) |
| Elmos | Robert Bosch (2) | Thomson Microsonics |
| Ericsson Components | SC300 (4) | ZMD (4) |
| Organizations | ||
| I300I | SELETE | MEDEA |
Strategically, a phased approach has been adopted to funding equipment assessment in SEA. This approach, when added to existing programs, has resulted in a portfolio of European Community funding options covering advanced research, equipment development and assessment of productivity issues for both 200 mm and 300 mm European equipment.
Of the first 43 projects in the SEA initiative, 15 are on 300 mm equipment: eight in beta assessments at user sites and seven in alpha tests at equipment company sites (Table 2). As yet there are no operational 300 mm production facilities in existence at IC manufacturers' sites. The SC300 activity in Dresden (also involved in SEA) is the first worldwide, while the second (in Europe) is likely to be at ST, Crolles, in France.
| Table 2. 300 mm SEA Projects | ||||||||
| 300 mm SEA projects - Evaluation at user sites | ||||||||
| Theme | Equipment supplier | Users | Project | Acronym | ||||
| Hot process | ASM International | SC 300, WACKER | 300 mm vertical furnace system | FASE | ||||
| Metrology | Philips Analytical | GRESSI, ST, SELETE, I300I | Fully automatic ellipsometer for 300 mm wafers | FLASH PT300 | ||||
| Cleaning | DMS | ST, I300I | 300 mm pod and open cassette centrifugal cleaner | CFC | ||||
| STEAG MicroTech | GRESSI, IMEC, ST, SC300, Wacker | Oxidation and epitaxy pre clean | OXEPICLE | |||||
| Automation | RECIF/INCAM | ST, I300I, Intel | 300 mm front opening pod and cassette sorter | POCS | ||||
| INCAM | SC 300, ST, I300I, SELETE | Tool for test lots logistics | TTL2 | |||||
| Test | Karl Suss | SC 300, TI, FhG- IIS-B | Automated 300 mm prober system | AUTOPSY | ||||
| Analysis | GEMETEC | AMD, IMEC, TI, Philips, ST | Surface analysis of Si wafers with VPD for TXRF | SUPRA | ||||
| 300 mm SEA demonstration tests | ||||||||
| Hot process | STEAG AST | SC 300, GRESSI | RTP implant annealing | IMAN 300 | ||||
| Etch | SEZ | I300I | Single wafer front and backside etcher | WM 303 | ||||
| Lithography | JENOPTIK | SC 300 | High throughput low CoO, low damage batch asher | RAPID | ||||
| FAIRCHILD | GRESSI | Lithography coat, develop, bake modules | CROWNS | |||||
| Cleaning | Contrade | SC 300 | Non contact, post-CMP wafer cleaning | STEAM | ||||
| Automation | Peter Wolters | iSi Tek | Double sided polishing for wafer reclaim | POL 300 | ||||
| RECIF | GRESSI | Single pick a place sorter with OCR | PMSPP 300 | |||||
New projects
SEA activities now continue under the EC Information Society Technologies (IST) program covering the period 1999 to 2002. The SEA strategy continues with its open, international approach with phased and flexible programs that can respond to industry trends and needs. It bridges the innovation-productivity gap by assessing equipment that addresses the next-generation technologies at the 0.15 µm level and beyond while providing solutions that can impact productivity, including 300 mm equipment.
To date, 11 new projects have been approved in the year 2000, with six having started in the domains of IC, microsystems and advanced assembly (Table 3). More project proposals are currently being reviewed for projects that will commence in 2001.
| Table 3. First Projects Started in IST | ||
| Domain Microelectronics | ||
| Advanced Process Control for 300 mm Plasma Production Processes | (APC 300) | |
| Participants: | ||
| Equipment supplier: | ASI (D) | |
| Evaluation site: | SC300 (D) | |
| IC partners: | AMD (D), Infineon (D), ST (F) | |
| Invited guests: | ||
| IC companies: | Fujitsu (J), IBM (USA), Infineon (D), Lucent (E), NEC (J), Sematech (USA) | |
| Equipment companies: | Applied Materials (USA), LAM (USA), TEL(J) | |
| Start/duration: | 1st January 2000/18 months | |
| Advanced Lithography using ArF wide field Step&Scan system | (ALASCA) | |
| Participants: | ||
| Equipment supplier: | ASM Lithography (NL) | |
| Evaluation site: | IMEC (B) | |
| IC partners: | AMD (USA), Cypress (USA), Infineon (D), Intel (USA), Philips (NL), Micron (USA), Motorola (USA), TI (USA), Selete (J) | |
| Invited guests: | ||
| IC companies: | IDT (USA) | |
| Equipment companies: | Lambda Physik (D), TEL (J) | |
| Start/duration: | 1st January 2000/12 months | |
| Oxidation and Epitaxy Pre Clean | (OXEPICLE) | |
| Participants: | ||
| Equipment supplier: | STEAG MicroTech(D) | |
| Evaluation site: | GRESSI (F) | |
| IC partners: | IMEC (B), STMicroelectronics (F), SC300 (D), Wacker Siltronic (D) | |
| Start/duration: | 1st March 2000/15 months | |
| Surface Measurement system with integrated TXRF | (SUMMIT) | |
| Participants: | ||
| Evaluation site and Equipment supplier: | GeMeTec | |
| IC partners: | IMEC (B), STMicroelectronics (F) | |
| Start/duration: | 1st January 2000/6 months | |
| Domain Microsystems | ||
| System and Process for deep etching with a double etch rate | (I-SPEEDER) | |
| Participants: | ||
| Equipment Supplier: | Alcatel Vacuum Technology (F) | |
| Evaluation site: | Robert Bosch GmbH (D) | |
| IC partner: | PerkinElmer Optoelectronics, GmbH IC (D) | |
| Start/duration: | 1st March 2000/16 months | |
| Domain SUB SYSTEMS (Assembly) | ||
| Anisotropic Conductive Film (ACF) die bonder assessment | (AFIDA) | |
| Participants: | ||
| Equipment supplier: | Cybernetix (F) | |
| Evaluation site: | Thomson Microsonics (F) | |
| IC partner: | Celestica (UK) | |
| Start/duration: | 1st January 2000/18 months | |
Projects already underway
Project ALASCA assesses the first-generation ArF wide-field step-and-scan system from ASML. Next-generation ArF lithography (193 nm) is expected to take over from KrF (248 nm) for 0.13 µm production required by the year 2002. The time available between introducing 193 nm step-and-scan systems into the market and inserting 193 nm into large-scale manufacturing is half of what occurred for 248 nm lithographic technology. To achieve this transition, a large consortium with a complementary range of skills has been assembled, including advanced semiconductor manufacturers from Europe, the United States and Asia.
The project has two phases for this R&D or pilot-line production tool. Initially it targeted the 193 nm issues in terms of general imaging capability and stability of the optical components under extended exposure conditions for 0.15 µm technology. The second phase began with performance upgrades and evaluation of the lithographic performance of the 193 nm step-and-scan system in terms of imaging capability, alignment and overlay, illumination, and exposure dose control, with ever-improving resists. Overlay is being looked at on difficult process layers (e.g., CMP), comparing the new ASML ATHENA alignment system with the prior "through-the-lens" alignment system.
Project APC 300 assesses the incorporation of the latest in situ diagnostic OEM equipment from ASI (Hercules/APC tool) into an integrated advanced technology subsystem for total monitoring of important plasma etch processes for IC fabrication. Monitoring is based on a novel technique - Self-Excited Electron Resonance Spectroscopy (SEERS) - that characterizes the internal condition of the plasma and provides a measurable value that quantifies the state of the interaction between the electrons and process gas. In effect it gives a fingerprint of the process indicating the possible drifts of the tool and potential variations (failures) in the wafer history. It allows inspection of the plasma processes in terms of absolute values, providing information on tool stability, matching, process transfer, deviation, in-homogeneity and chamber condition.
Success in the project will be measured initially by the ability of all the global IC partners to introduce real-time process control using the APC advanced sensor technology diagnostics at a modular level for their plasma processes. The Hercules/APC is being evaluated, in situ, on leading-edge plasma systems including Applied Materials and TEL etchers. Finally, the evaluation site will not only monitor its plasma processes in real time but also incorporate the resulting data into a universal APC framework for various etch systems. A measure of the success of this will be the extent to which the APC structure and its associated data network (LAN) are operational at the end of the project. The system's cost-effectiveness will be demonstrated by evaluating its impact on wafer usage, yield and the host equipment's manufacturing metrics. An attractive return on investment (ROI) is anticipated.
Project OXEPICLE assesses the STEAGMicroTech 300 mm wafer cleaner for surface preparation prior to key process stages including gate oxide, low-temperature silicon epitaxy and SiGe alloy heteroepitaxy or deposition. The equipment can currently perform "standard" cleaning, but there also is a requirement for reproducible hydrophobic and hydrophilic surfaces at low cost. Hydrophobic surfaces, for instance, are required for emerging low-temperature CVD processes, epitaxy/hetero-epitaxy, while polycrystalline, thin oxide and even interfacial oxides need hydrophilic surfaces in order to master the nucleation effects that influence surface roughness. Also targeted is the generation of processes with low chemical consumption to address economic and ecological goals.
The success of the process recipes will be evaluated by analyzing the cleaning solutions used in the machine and also the treated wafer surfaces in typical and more stringent processes. One application will be high-quality thin dielectric gates in CMOS technology, where the thin oxide is multi-process in nature, with oxidation and nitridation processes each requiring different cleaning treatments. Similarly, silicon and SiGe alloys are required for improved performance in advanced bipolar and buried-channel CMOS technologies. These must be performed at relatively low temperatures. Strategic issues for future 300 mm fabrication plants also will be considered, not only from the point of view of cost and waste management but also the relevance to clustering, flexible manufacturing and rapid cycle time.
Project SUMMIT assesses the requirements for the next-generation 300 mm in-line wafer surface analysis with integrated TXRF. For this purpose GeMeTec has introduced numerous innovations for a new TXRF analysis module for the analysis of residues from VPD droplets relating to the substrates employed and the analysis of lighter elements.
The main objective of this project is to test these innovative features of the new instrument as a preliminary step before a beta-site evaluation. Within SEA this type of project is called a "proof of concept" equipment test, whereby new concepts and applications may be evaluated at the equipment company's facility prior to placement for a full SEA project at a mainstream user site under "close to production conditions."
Currently, VPD sampling is carried out mainly on silicon wafers. However, for 300 mm wafers the footprint of a TRXF module is too high for integration in a VPD system. To avoid the unnecessary waste of space it is proposed to use smaller, non-silicon substrates - e.g., 50 mm quartz substrates that can be used repeatedly. As preferred in this system, these could be low-cost disposable polymer substrates (e.g., 50 mm diameter PMMA and polycarbonate disks).
Another major drawback of TXRF is its lack of sensitivity for detecting the lighter elements, particularly Na and Al. Such measurements must be accommodated to maximize the advantage of a totally integrated system. This is addressed within the new TXRF module by splitting the analysis in a low-energy measurement with excitation by CrKa and high-energy measurement by excitation with WLb or MoKa. The system has separate TXRF chambers, optimized for the chosen energy ranges.
Finally, the addition of a known amount of an element to the droplet (internal standardization) has been introduced to provide an elegant means to compensate for non-homogeneity and other geometry effects in the droplet residue.
Project I-SPEEDER evaluates an advanced, high-rate, deep reactive ion etch (DRIE) tool for silicon micromachining from Alcatel. A schedule of hardware and process upgrades is targeted to double the etch rate (from 4 µm/min to >8 µm/min), improve uniformity across wafer area by a factor of 2 and improve profiles by a factor of 2. It also is intended to reduce the edge exclusion zone of the wafer from 10 mm to 5 mm by implementing an electrostatic chuck for holding the substrate.
This project is addressing high-rate, high-aspect-ratio, "through wafer" and silicon-on-insulator etching for power semiconductor fabrication, MEMS, and deep etched holes for fabrication of silicon heads for data storage or through the wafer interconnects.
It is predicted that the equipment and process enhancements will allow the replacement of classical wet etch-related manufacturing technologies currently used for established products, and provide the enabling technology for the new etch requirements for the enhanced and emerging component and microsystem products in the future.
Project AFIDA evaluates the performance of the Cybernetix flip-chip die bonder specifically designed for chip assembly processes using anisotropic conductive film (ACF). The modular-based design provides a complete system for ACF preform cutting/positioning, die handling/alignment relative to carrier substrate, and final press bonding. Compared to the existing ACF machines, it includes unique and innovative features such as complex shape ACF cutting and ACF laminating to the active surface of the die.
While the equipment is designed primarily for very high-volume, high-quality, low-cost flip-chip assembly of miniaturized surface acoustic wave (SAW) filters, as for example used in mobile phones, the innovative system concepts also are compatible with a wide range of other potential applications with similar needs. Examples include: sensitive devices such as CCDs, sensors or microsystems that require a space made between chip and package, chip assembly in cavity packages or other complex shape type of substrates (3-D packaging, molded circuits etc.). Conventional silicon chip assembly, for which ACF techniques have not been used significantly to date, also is made possible by this approach.
The assessment will be done in a specialized back-end production equipment facility that is used as a precursor for installation of back-end equipment in production lines worldwide. The application areas include those for most advanced-generation products including: cellular phones, medical products, rf/wireless products, high-speed, single-chip and multi-chip modules.
Soon-to-start projects
In Project ATOL, an international consortium is to evaluate the production worthiness of the ASMI atomic layer chemical vapor deposition (ALCVD) cluster tool for barrier and Cu seed multilayer applications in 0.13 µm manufacturing and beyond. The evaluation site is IMEC with partners AMD, Infineon, Philips and Sony. The results will be compared with those obtained from current ionized PVD and CVD production methods.
Project MESA evaluates a microcalorimeter-type EDX system from CSP Cryogenic Spectrometers GmbH that is based on superconducting, thin-film technology. It enables fast, high-resolution, highly sensitive measurements with resolutions of 10-15 eV that are not achievable with conventional EDX detectors based on semiconductor detector systems (130 eV). This is a quantum leap in performance and will provide the semiconductor industry with the only practically feasible solution for routine microanalysis when proceeding to smaller feature sizes.
The results obtained with microcalorimeter-type EDX detectors will be compared with those obtained by conventional EDX and WDX analysis systems, and the reliability of the system and its capabilities will be evaluated at Infineon Technologies with AMD as a partner.
The overall objective of ILSIMS is to assess a new industrial in-line SIMS with the potential to provide the first SIMS equipment for in-line control in integrated circuit manufacturing. The work will result in full 300 mm wafer analysis capability, very large sensitivity at high depth resolution, and a capability of SIMS analysis on patterned wafers. The re-use of monitor wafers will be studied and cross contamination suppressed via specifically developed masks. The equipment will have a high degree of automation and user-friendly software. Reliability and cost-of-ownership issues will be particularly addressed. The consortium includes STMicroelectronics (evaluation site) and Siemens/Infineon. Lucent (USA) and Samsung are providing complementary work in close cooperation with the equipment supplier Cameca. The research institute IRST(I) also is participating.
Again there are new projects on assembly (EXCEL) and microsystems (MICROSPECT), details of which will be available shortly on the SEA Web site.
Jeff Bruchez has worked in the microelectronics industry for 33 years, holding senior positions in R&D, IC manufacturing and with semiconductor equipment companies. He is now an independent technology consultant, director of SEA dissemination and responsible for the team of independent experts who participate in the monitoring, evaluation and dissemination of SEA and SEA300 projects. He also is a member of the Microelectronics Advisory Group (MAG) to the EC. Further details on SEA can be obtained from: SEA Dissemination Office, Central Microstructure Facility, Rutherford Appleton Laboratory, Chilton, Oxfordshire OX11 0QX, UK.Phone: +44 1235 445946
Fax: +44 1235 446174
