New SECAP Consortium Steps Into WLP Void
John Baliga, Associate Editor -- Semiconductor International, 10/1/2000
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The consortium's purpose is not to ensure a supply of tools so much as to ensure that all wafer-level packaging (WLP) equipment and technology work in harmony. WLP is one of the fastest-growing areas of packaging technology, and it can be viewed as an extension of front-end wafer processing. The many companies now performing WLP include semiconductor companies, packaging foundries and third-party WLP-only providers (See "Wafer-Level Packaging Has Arrived"). In this type of environment, where any of three types of companies can perform some or all of the steps, a high degree of coordination is a must. If a semiconductor manufacturer integrates WLP with its own wafer processing efforts, all the coordination is done within that company. It's when more than one company is involved that "hand-off" errors can occur.
As the semiconductor industry moves to 300 mm wafer processing, front-end processing is still receiving the lion's share of the focus. The 300 mm transition coincides with an emergence of packaging and interconnect as the performance-limiting part of an IC, as well as the emergence of wafer-level packaging. Development of packaging technology, and especially WLP technology, cannot take a back seat to developing front-end wafer processing technology. Though front-end processing has more difficult challenges, a poor packaging process, or poor coordination with packaging processes, can neutralize the gains made on the front end.
The SECAP consortium will be a benefit because "it will harmonize the different types of systems and processes used for advanced packaging," according to Dietrich Toennies of Karl Suss. Instead of buying into individual steps, a company looking to perform WLP would buy into a process sequence. Toennies continued: "The lithography process, for example, cannot be addressed independently from photomask technology and metalization techniques. All processes influence each other, and it is important that the different types of systems are in harmony."
A year ago, Tom DiStefano made statements consistent with the main thrust of SECAP when he formed Decision Track. He noted that equipment and materials were not the gating items in forming an infrastructure for chip-scale packaging (CSP) technology, but that information is.
Karl Suss and Image Technology are well-known companies in the packaging arena. Semitool and Unaxis (formerly Balzers Process Systems and Plasma Therm) are better known for front-end processing, though they have provided tools for WLP and other packaging processes.
Amkor/Cadence SiP Alliance Announced
Amkor Technology (Chandler, Ariz.) and Cadence Design Systems (San Jose, Calif.) recently announced their alliance to develop a system-in-package (SiP) design flow. The alliance actually was formed in February, and Cadence provided some consultancy along with its advanced packaging design products.
Amkor has expressed the intention to provide close coordination between chip design, package design, manufacturing and test development using its SiP module prototyping line. This type of coordination has been done before in multichip packaging applications. However, doing this with high volumes and commercial market cycle times is only now starting to emerge in the industry.
In addition to having working relationships with various semiconductor companies, Amkor has a wafer fab of its own in Buchon, Korea. The company may be able to develop the high degree of coordination after it is completely on its own, which could make a difference in the success of its SiP process.
