Inspecting Bumped Wafers: What You Should Know
Bernie Adams Electroglas Inspection Products, Corvallis, Ore. -- Semiconductor International, 10/1/2000
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At a Glance | | |
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Bump defects are bad news. Bumps that are too tall or irregular can bend probes on probe cards, which can cost $60,000 each, and incur substantial costs for tester downtime and repair labor. Besides causing mechanical damage, malformed bumps and extraneous bump material can bridge power and ground contacts, resulting in excessive current draw through a probe card. The 1999 Roadmap1 projects chips eventually will draw 140 A each at 1.2 V. Optical inspection before probing will be imperative to avoid probing shorted bumps at high current.
If not flagged by inspection, bumps that are too large, small or altogether missing can pass through probing without incident and lead to device failures. This wastes test and packaging time in addition to materials, and introduces the chance that an IC with a bad bump will function correctly through final test but fail in a customer's system. Inspection after wafer probing is needed because probing can damage bumps - especially on wafers with high bump counts, which require high vertical forces during testing in order to seat probes for proper contact.
Some examples
The ability to trace the cause of defects within bumping processes is crucial for yield management. In one recent case involving C4 wafers, the ability to archive and correlate defect data over distant, non-sequential wafers allowed the fab to identify and fix process problems that otherwise would have been extremely difficult to isolate. Bridged bumps were detected on several wafers; but among those wafers, the bumps that were bridged were not the same on every wafer. By comparing and superimposing the locations of the defects, however, the inspection system revealed the bridged bumps fell on a straight line from wafer to wafer (Fig. 1). The analysis led to the source of the defects: a tiny crack 2-4 cm long in the C4 mask associated with those wafers, which had been missed during mask inspection.
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| 1. Note the superimposed defect locations in the upper left quadrant along a straight line intersecting several die areas. |
By archiving, tracking and analyzing bump data over many replicated wafers, inspection tools have graphically shown a tendency of the C4 process to slightly displace bumps near the perimeter of wafers from their ideal locations. Although that process of evaporative deposition generally results in highly uniform bump composition and volume, bump registration on die near the wafer edge must be closely monitored. The cause of the slight misalignment is mask creep relative to the wafer, due to the differential in thermal expansion between the molybdenum mask and the silicon.
In another situation, involving a stencil bump process, an inspection system identified variations in bump volumes across wafers in a consistent pattern among die. By automatically aggregating and converting bump height measurements along columns and rows of die into mean values, then displaying those column and row values as bar graphs, the pattern became immediately evident (Fig. 2). The graphs showed bump mean heights progressively increased from the wafers' centers outward. As a result of that display, the variation in bumps became easy to trace to sag in a stencil, which nearly closed the openings at the center of the stencil.
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2. Plots of mean bump height along perpendicular axes on a wafer led bump-process engineers to identify a sagging stencil. |
Yet another problem with a screen process was determined by correlating a pattern of satellite material from wafer to wafer. The coincident wafer defects were traced to microscopic tears that were not evident during routine inspection of the screen.
Sources of bump defects
Defects stem from various problems in bump processes, but the most frequent source is mask flaws. For example, the C4 evaporative process employs molybdenum masks that are usable only for a limited number of wafers.2 After each use, a mask is cleaned, examined and placed in inventory for reuse. At any time, a line may have dozens of masks in service. The masks contribute the largest portion of the cost per wafer for the C4 process.
Obviously, the longer a mask can remain in service, the lower the wafer cost. The mask inspection tools in common use are very good, but culling a defective mask depends on an operator's attention and skill. Some mask flaws are nearly indiscernible to the most trained eye, and a mask that is free of residue after cleaning can still become contaminated before reuse.
Automating bump inspection
To maintain high throughput, automated inspection and defect classification is imperative. Especially for complex circuits that incorporate tightly packed bumps, manual inspection is tedious, slow and error-prone. Metrology tools used in the characterization of front-end wafer processes certainly could provide extremely accurate measurements of bump profiles, but could never inspect all the bumps on wafers at a rate approaching that required for production volume. Automated inspection systems must find and measure abnormal bumps, categorize the abnormality, plot their location, create a wafer map of bump defects to isolate bad die so they will be skipped during probing, and archive the data for continual process analyses.
Determining the exact causes of bump defects requires a very large database for archiving measurements and images, as well as tractable programs for correlating, analyzing and presenting the information. Certain repetitive bump defects recur only infrequently among wafers and would be construed as random anomalies if they could not be linked to distant incidents.
Tracing bump defects to the mask that caused them can also be difficult because of the intervals between mask use. A CVD chamber usually holds fewer than the 25 wafers in a typical lot, making the correspondence between a particular mask and particular wafers over time complicated to establish, unless there is a very good system for data collection, analysis and management.
Field results
The case histories reported involved results obtained by the use of an automated, optical bump inspection system and related data-analysis tools developed by Electroglas Inspection Products (Corvallis, Ore.). The systems inspect, measure and analyze electroplated bumps, as well as C4 and printed bumps, with the same accuracy, after tuning for the properties of bumps that are ideal to the particular process.
The QuickSilver bump inspection system employs structured lighting and a time-delay-and-integration camera similar to those used in front-end metrology instruments to reveal slight deviations from the contour and reflectivity of an idealized bump. After a short training period to tune the system for a particular product, bump dimensions are measured with an accuracy nearly that of precision engineering metrology tools but at a throughput of 30 wafers/hour with 100% inspection coverage, regardless of wafer size, number of bumps or bump pitch. The system enables production engineers to view bump measurements, along with various wafer maps and images of die, wafers and individual bumps, in various combinations and formats (Fig. 3).
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| 3. A Y-offset contour map highlights bumps that drifted from their ideal position. An X-offset map similarly would present bump displacement along the perpendicular wafer axis. |
For statistical process control, aggregate data and trends are more valuable than measurements of individual bumps. To provide trend data on the basis of the inspection unit's measurements of individual bumps, the workstation calculates mean bump volume averaged over die, wafers or lots, and presents the information to bump process engineers in the form of SPC charts and reports.
Conclusion
Bump inspection is rapidly becoming a critical issue. According to a 1999 Prismark report, by 2002 more than 2.3B flip-chips will be produced annually. Of those, 16% will have more than 400 bumped I/O connections.3 Microprocessors already in production have more than half a million CVD-applied or electroplated bumps per wafer. As bump pitch decreases and new handling equipment comes on-line, the total number of bumps per 300 mm wafer will exceed 1M. By the bumping stage, such expensive wafer products will have acquired nearly their entire value, and their worth will ride upon how strictly the bumping process can be monitored and controlled.
Wafer bumping requires dedicated new inspection methods to ensure profitable yields. Qualifying bumped die and maintaining bumping processes requires optical inspection of every bump on every die on every wafer. Bump planarity, volume, shape and presence must be evaluated on the fly at production speed, and compared wafer to wafer and lot to lot, so that solder-mask or stencil defects and other process anomalies can be identified immediately. .
Bernie Adams is vice president of sales for Electroglas Inspection Products. Prior to joining the company, he was director of worldwide sales for Flip Chip Technologies, a joint venture of Delphi (formerly General Motors) and Kulicke & Soffa that provides wafer bumping and processing services.REFERENCES
- Semiconductor Industry Association, "The International Technology Roadmap for Semiconductors: 1999."
- J. Franka, K. Glessner, D. Wontor, "Solder Bump Technology: Present and Future," Semiconductor Fabtech, May 1995.
- Prismark Partners LLC, "Global Flip-Chip Bumping Analysis," Report No. 1213, March 1999.
