Abrasive-Free Chemical Polishing Could Improve Yields
Laura Peters, Senior Editor -- Semiconductor International, 10/1/2000
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After fabricating the CMOS and bipolar transistors on a bonded SOI substrate, the researchers deposited SiO2 by HDP-CVD and performed a pre-metal CMP. The tungsten contacts and local interconnect were fabricated using standard subtractive methods. On M2 through M5 levels, single-damascene copper was used with tungsten vias. After trench etching each layer, a low-pressure, long-throw sputtering process deposited both the TiN barrier and copper seed layer and fill; this was followed by reflow. Next came a two-step polishing process using AFP with a hard polyurethane pad, IC1000 from Rodel (Phoenix). A nitride barrier cap was deposited using a NH3 plasma treatment to reduce CuO to Cu at the metal surface. The top two metal levels were fabricated using standard aluminum subtractive etch patterning. The researchers analyzed resulting defects and corrosion using a 2138 wafer inspection tool from KLA-Tencor (San Jose, Calif.) and a SEM review tool from Applied Materials (Santa Clara, Calif).
Because the AFP solution only removes copper chemically, there is virtually infinite selectivity to the underlying TiN barrier. The barrier film was polished by CMP with an abrasive slurry having high selectivity of TiN removal to copper and SiO2. Tungsten plug polishing with the AFP process left no metal residue. The only defects detected after processing 18 wafers were common defects from film deposition and patterning processes. The conventional yield management system appears to work well for this damascene process.
The new abrasive-free process also was instrumental in increasing TDDB (time-dependent dielectric breakdown) lifetime between copper interconnects in the same layer, possibly due to reduced damage to oxide layers during polishing. The group measured the lifetime at 140°C using comb line capacitor test structures, measuring the time until leakage current exceeds 1µA/cm2. The researchers determined the longer TDDB lifetime was the result of both the AFP process and the addition of the NH3 plasma process. Conversely, a traditional CMP approach is more likely to damage the SiO2 interlevel dielectric. Finally, tests showed corrosion resistance improved by isolating the wafers through the copper polishing and post-polishing cleaning steps. This prevents photo irradiation from reaching the wafers and stimulating copper corrosion.
In a separate characterization of the AFP process, Hitachi's researchers found erosion and dishing were one-fifth the depth of that produced with conventional slurries, even with 100% overpolish across widely spaced features. SiO2 erosion was negligible. The reduction in polished depth directly affected the reduction in electrical resistance of the copper interconnects (by 15%); but more importantly, the resistance deviation was reduced to less than half that obtained by conventional CMP. In this study, the TiN and TaN barrier metals were removed by RIE using SF6 gas.
By eliminating factors that commonly cause CMP defects such as scratching, pitting and particle agglomeration, the new abrasive-free polishing process represents a promising technology for copper interconnect fabrication.
