Wafer-Level Packaging Has Arrived

Dr. Philip Garrou, IEEE Components, Packaging and Manufacturing Technologies Society -- Semiconductor International, 10/1/2000

In wafer-level packaging (WLP) technology, the die and "package" are manufactured and tested on the wafer, prior to singulation. This makes it different from all other package types. The area it occupies when mounted onto a printed wire board (PWB) or other substrate is the size of the die. Since the size of the package and the size of the package mounted on a substrate equal the size of the die, all true wafer-level packages (WLPs) use solder balls (mainly in area array) to interconnect the package to the board.¹ One example of WLP technology is the microSMD package (Fig. 1) from National Semiconductor (Santa Clara, Calif.).

Wafer-level packaging technology has evolved from the solder bumping technology introduced by IBM for mainframe System 360 in 1964. Since that time, with the exception of Delco and a few other companies, solder bumping technology has been confined mainly to high-end ceramic packaged functions.

In 1992, Tsukada of IBM Japan published that bumped chips could be attached directly to PWBs if the chips subsequently were underfilled.² This announcement drove the packaging community to take a hard look at this technology for consumer products. Since then, two trends have continued to drive the implementation of solder bump interconnect: (1) the continuing drive to higher densities on chip, resulting in the need for more I/O; and (2) consumer demand for continued miniaturization and increased functionality in handheld and portable products.

Nomenclature issues

There is significant confusion in the industry over the nomenclature that surrounds so-called wafer-level packaging. If one sticks to the simple definition that "all packaging and interconnection must be fabricated on the wafer prior to dicing," then simple bumped chips can be looked at as wafer-level packages.

Differentiation comes when one looks at whether the devices are packaged further prior to assembly. For high I/O microprocessors and ASICs, the chips are mounted on chip carriers before final surface mount attachment; these are not wafer-level packages. Smaller die and/or die with low I/O can be mounted directly on the final substrate; thus these are wafer-level packages. In most cases, the same technology is used for bumped chips and wafer-level packages. Most recent foundry announcements offer both "bumping" and "wafer-level" or "chip-scale" services.

1. The microSMD package is an example of wafer-level packaging technology currently in production. (Source: National Semiconductor)

The size of the solder ball or the technique to deposit the solder should not be used to determine whether the devices are wafer-level packages. The solder ball size is determined by the final device reliability requirements, which in turn are determined by the size of the chip and the number of solder balls, among other things (discussed later). A lot of wafer-level packages use 0.5 mm preformed solder balls on the area array solder pads. Many believe a true wafer-level package does not need underfill after assembly, but there are now so many telecommunication exceptions to this that it should not be used as a criterion.

WLP economics

When foundries are running at full capacity, WLP cost is expected to be lower than for traditional packages. Cost reduction in IC manufacturing traditionally is achieved in two ways: increasing wafer size (which results in more die per wafer) and decreasing feature size (which results in more chips on a given size wafer). This is true because wafer processing costs remain about the same as the wafer gets larger or the die get smaller. In reality the equipment required for larger wafers is more expensive; but the cost of the equipment is more than offset by the increased production capacity. This is typically not true for chip packaging. As the number of die per wafer increases, one must linearly increase the number of wirebonders, molding machines, testers and handlers, thus increasing the back-end costs with the increased number of die.

Since wafer-level packaging is processed on the wafer, it realizes the same advantages as ICs: the packaging cost for WLP will go down as wafer size increases and/or IC size decreases. Major economic savings occur when packaging and test are done before the wafer is diced. In addition, savings in areas such as materials consumption, international transportation and equipment purchases will be achievable if WLP is instituted on a broad scale. Wafer-level packages ship in standard tape and reel, and are assembled by standard SMT technologies.

Wafer-level packaging does have a few disadvantages. Since the interconnect must be located under the die, very high I/O die would require very small solder balls on very tight pitch. Although it is technically feasible to manufacture very small solder balls (down to 50 µm), they would require very high-density PWB to interconnect the I/O. Such microvia PWBs are very expensive. The tightest board pitch currently in use is 0.5 mm.

It also is clear that all the die, good and bad, are "packaged" in wafer-level packaging schemes. Thus, early on in the production cycle, when yields are low, wafer-level packaging exacts a penalty for packaging all the chips.

While all current wafer-level technologies result in packaged solder bumped chips, the technologies differ, sometimes significantly, in processing steps.

Redistribution technologies

Most ICs(>95% of manufactured die), with the notable exception of advanced microprocessors, are still designed with peripheral pads. The peripheral pad pitch is decreasing down to 70 µm due to the increasing number of I/Os. Wire bonding tools will handle this pitch, but the high-density boards required to handle this pitch are far too expensive for commodity products.

Most options proposed for low-cost, wafer-level packaging 18 months ago have fallen by the wayside. By far the majority of WLP processes in practice now(>90%) are of the redistribution type. Commercial foundries and users are listed in Table 1. Announced commercial foundries are noted.

Table 1. Redistribution Technologies for Wafer-Level Packaging
Company	Technology	Materials	Solder ball technology	Activity level
USA
FCT	Ultra CSP	Al/NiV/Cu; BCB	Screen print; place	foundry; shipping
Unitive	Xtreme CSP	Al or Cu; BCB	Plate; place	foundry; shipping
Dallas Semi	Unitive licensee	Al; BCB		commercial; shipping
Xicor	FCT licensee	BCB		commercial; shipping
National Semi	microSMD	BCB		commercial; shipping
Atmel	dBGA	BCB		commercial; shipping
CMD	FCT licensee	BCB		limited shipping; full commercial 4Q 2000
Alpine Micro Systems		Cu/BCB		limited shipping
MCNC		Al or Cu; BCB	Plated	prototype only
Europe
TU Berlin		Cu/BCB	Screen print; place	licensing &prototype only
IMEC		Cu/BCB		licensing & prototype only
CS2	IMEC licensee	Cu/BCB		foundry under construction
Taiwan
APack	AT&T licensee	Al/PI		limited production; foundry
Unitive Taiwan	Unitive licensee	Al or Cu; BCB	Plate; place	foundry; under construction
ASE	FCT licensee	Al/NiV/Cu; BCB	Screen print; place	foundry; under construction
SPIL	FCT licensee	Al/NiV/Cu; BCB	Screen print; place	foundry; under construction
Chipbond	chipCSP	Cu/BCB		foundry; limited production
Korea
Amkor	FCT licensee; Unitive licensee	Al/NiV/Cu/BCB; Al or Cu/BCB	Screen print; Place, plate	foundry under construction
Hyundai	OmegaCSP	BCB + elastomer		development
Japan
Oki/Casio		T/NiCu; PI		foundry; limited production
Fujitsu /Shinko	Super CSP	Ti/NiCu; PI		foundry; limited production

2. Redistribution of I/O pads is a typical component of area-array WLPs.

Redistribution is shown in Figure 2 in cross section. Such redistribution requires thin-film polymers (secondary passivation) and metalization to reroute the peripheral pads to an area array configuration, and under bump metallurgy (UBM) to create reliable solder joints. Benzocyclobutene (BCB) or polyimide (PI) typically are used as the dielectrics. Aluminum or copper is used as the rerouting metalization. The original IBM technology used "phased" CrCu as the under bump metallurgy, and it had been thought that this was a prerequisite for reliable solder joints. Intel recently put that notion to rest with the commercial announcement of TiNi UBM.

Figure 3 shows a typical redistribution process used to define an area array pattern. The perimeter pads are rerouted to area array using Cu traces and BCB dielectric; UBM is sputter deposited, and solder paste is screen-printed and reflowed.

3. A typical redistribution process includes copper conductors and a dielectric such as BCB. (Source: Fraunhofer IZM/Technical University of Berlin)

Redistribution technology offers chip protection (environmental and mechanical) based on the polymer dielectric coating used in its fabrication. Much of the commercial production going into place, as shown in Table 1, is using BCB dielectric³ due to its low curing temperature, rapid thermal curing, low water absorption, compatibility with copper and superior environmental protection. This was evidenced by surface insulation resistance, leakage current and triple track testing recently published by Georgia Tech.⁴ Redistribution allows peripheral pad pitches to be reconfigured into area arrays having significantly larger pad pitches, allowing interconnection on less costly, less complex PWBs. When rerouting is not needed in low I/O devices such as shown in Figure 1, "redistribution" technology is still used. A polymer layer is deposited to serve as a permanent resist for subsequent deposition of the UBM.

Commercialized redistribution technologies

The FCT Ultra CSP technology is based on simple redistribution technology. It uses Al/NiV/Cu metalization for redistribution and BCB as the interlayer dielectric. Both eutectic and high-lead solder balls are screen-printed or placed as preformed solder balls. Lead-free solutions are available. FCT redistribution technology has been licensed by ASE (Kaohsuing, Taiwan), SPIL (Taichung, Taiwan), California Micro Devices (Milpitas, Calif.) and Amkor (Chandler, Ariz.).

The Fujitsu Super CSP is shown in cross section in Figure 4. Redistribution to area array is achieved using Ti/Ni/Cu metalization and PI dielectric. Cu posts are then plated (100 µm) on the area array pads, and Ni/Pd barrier layers are plated on top of the posts. Molding resin is used to protect the surface and distribute the stress. Preformed solder balls are aligned to the exposed Cu studs, and transferred and reflowed on the CSP. The wafer is then diced into individual chips.⁵ This technology appears more costly than others because of the number of steps and the specialized molding equipment needed. This technology is being scaled up by Shinko (Nagano, Japan).

4. Fujitsu's Super CSP has copper posts added to the redistribution, which are embedded in a molding encapsulant. (Source: Fujitsu)

Oki (Tokyo) has described a technology very similar to Fujitsu. This is being scaled up by IEP (Tokyo), a joint venture of Casio and Oki.

Unitive's Xtreme CSP technology consists of a family of products that use Cu/BCB, solder or Al/BCB redistribution, a phased Cr/Cu or Ti/Ni UBM, and electroplated (up to 200 µm) or placed preformed(>250 µm) solder balls. They offer high-lead, eutectic and, starting in September, lead-free solder solutions. The company's technology has been licensed by Dallas Semiconductor, Unitive Taiwan and Amkor.

Chipbond chipCSP technology also uses a Cu/BCB redistribution and solder plating technology.

Glass "encapsulated" technologies

Shellcase CSP technology seals the chip between glass plates. The peripheral pads on the die are first extended into the dicing streets using Al/BCB interconnect. The face of the wafer is then glued to a plate of glass and the wafer backside lapped down to 100 µm thickness (total thickness of the resultant package is 0.3 to 0.5 mm). The backside of the wafer is sealed in glass and is partially sawn to expose the extended pads. The wafer is metalized and the area array leads defined by lithography. UMB is deposited and defined, bumps attached and reflowed, and the die tested and diced. This technology appears best suited for optical applications such as the incorporation of filters and lenses, which allows the fabrication of devices such as image sensor chips.⁶

Table 2. Thermal Cycle Reliability Results (-40ºC to 125ºC)
Chip size (mm)	I/O	Solder ball size (mm)	Cycles to first failure
12	176	0.45	900
12	176	0.35	400
12	92	0.45	500

Flex tape technologies

Amkor has publicized its wsCSP technology, in which a redistribution pattern on Cu/PI flex tape is attached to the wafer with adhesive. The chip is connected by wirebonds from the chip pads to the film. Liquid encapsulant is used to protect the wire bonds and bond pads. The company recently announced, however, that it will not manufacture this package and subsequently has licensed the FCT and Unitive redistribution technologies for scaleup in Korea.

Others such as Tessera (San Jose, Calif.) continue to look at the technical and commercial feasibility of such flex tape-based processes.

Reliability

In a conventional leaded package, strains are relieved through the compliant gull wing leads. In area-array solder ball packages the strain must be relieved in the solder. The important mechanical variables are: (a) ball distance from neutral point (DNP), which is determined by chip size and bump pitch; (b) the bump standoff; and (c) the number of bumps. The greater the DNP (the further the bump from the neutral point) the greater the strain generated in the solder bump and on the underlying surface.

Such results are shown in Table 2. For a given 12 mm chip the best thermal cycle reliability is obtained for the larger solder ball and the larger number of I/Os.

An interesting deviation from the traditional redistribution-type wafer-level package is the recent disclosure by Fraunhofer IZM/Technical University of Berlin. Profesor Reichl and co-workers were the first group to propose the concept of wafer-level packaging in 1996.⁷ Their recent disclosure shows screen-printed solder balls can be covered in CTE matched "underfill" and mechanically polished to expose the solder balls, and then solder balls can be placed at these sites. This produces a solder ball stack that is ~2x the height of a normal solder ball, while the half "underfilled" structure distributes the stress on the solder columns and protects the redistribution layer from stress concentrations. This process is shown in Figure 5. Such structures reportedly show ~2x the cycles to first fail in thermal cycling studies.⁸

Applications

National Semiconductor recently announced a WLP known as microSMD.⁹ Figure 1 shows a wafer-level packaged die 1.45 x 1.45 x 0.8 mm thick. The solder bumps are 0.17 mm in diameter and 0.15 mm high. The solder bump UBM is deposited on a BCB repassivation layer.

Similar low I/O redistribution wafer-level packaging technology has been commercialized by Dallas Semiconductor (One Wire), Atmel (dBGA), Xicor (X-BGA), Bourns and several others.

6. Wafer-level packaging was used to make the substrate for this 2.4 GHz VCO. (Source: Intarsia)

Integrated passives such as resistor nets and thin-film RLC passive components also are turning up packaged in minimal wafer-level packages. To achieve the lowest cost and smallest available footprint, wafer-level packaging is being employed. Suppliers such as California Micro Devices (CMD), Bourns, Intarsia and AVX all have devices in or entering production. Custom Silicon Solutions, (CS2, Zaventem, Belgium), which currently does BGA assembly, recently licensed the bumping and thin-film passive component technologies of IMEC and has announced manufacturing of thin-film microwave components by spring 2001. Figure 6 shows a 7.8 x 4 mm, 2.4 GHz VCO produced by Intarsia.

Wafer-level test

Wafer-level burn-in and test is a must for the adoption of low-cost wafer-level chip-scale packaging (WLCSP). Companies such as FormFactor, Matsushita, Micronics Japan, and Gore/Motorola/Tokyo Electron have developed non-destructive probing technologies to deal with wafer-level testing and burn-in of bumped wafers (Table 3).

Table 3. Wafer-Level Burn-In and Test Technologies
Company	Technology
Form Factor	MOST, Microspring Contact
Micronics Japan	VS-contact, G-contact
Matsushita
WL Gore (Motorola/TEL)	GoreMate, Inferno

The FormFactor Microspring Contact is a controlled-shape and -height spring element (Fig. 7). The Microspring Contact has been used on probe cards to contact Al wirebond pads, Au pads and solder balls. It is reported that a customer has performed more than 2M touchdown and compression cycles on test cards without failure. The FormFactor technology has been proven in pre-production to allow on-wafer at speed testing (500 MHz) as well as full wafer burn-in (low speed, long cycle time) at full broad side contact. Hyundai reportedly has licensed this test technology for its DRAM manufacturing.

Contact between the substrate and wafer in the VS-contact technology from Micronics Japan is made by an interposer composed of conductive isotropic rubber and a flex polyimide sheet containing Ni-plated vias that match up with the bumped wafer surface.

7. Microspring contacts have demonstrated high performance and durability in wafer-level testing applications. (Source: FormFactor)

In similar fashion, the Matsushita technology consists of a polyimide membrane with Ni bumps and a pressure-sensitive, conductive rubber, which are fixed in a ceramic ring with TCE similar to the silicon substrate.

In the WL Gore technology, a z-axis conductive material (which can only be used once) is used as the contactor. It does not have to be patterned or aligned.

Underfill

There is general agreement that wafer-level packages are reliable without underfill for small die (DNP < ~2.0 mm). The reliability of large die (5-10 mm) without underfill depends on the application requirements.

Underfills are filled epoxy resins that are dispensed under an area array assembly to fully fill the area between chip and board. It generally is accepted that the underfill shares and reduces the solder strain level to ~10% of unencapsulated solder bumps. This is found to increase lifetimes in thermal shock accelerated life testing.

Although CSP assemblers would rather not underfill, since this process takes time and thus decreases throughput, most handheld devices contain underfilled WLCSP structures. It appears that twisting of PWBs with solder ball-mounted WLPs causes solder failure, and thus the assemblers use underfill as an extra precaution even when accelerated lifetime studies indicate there should be no problem. The recent development of fast-cure, no-flow underfill materials and full wafer transfer molding technology may make these options more attractive.

Conclusion

A few short years ago, true "wafer-level packaging" was seen as a technology to be practiced in the far-off future. In fact, wafer-level packaging has arrived, with volume capacity in place around the world as you read this article. While most capacity going into place is based on redistribution technology, there certainly is still room for alternate low-cost wafer-level solutions. .

Phil Garrou received his B.S. and Ph.D. in chemistry from North Carolina State University and Indiana University, respectively. He is global director of thin film materials in Dow Chemical's Advanced Electronic Materials business. His interests lie in the area of applying polymeric materials to the fabrication of microelectronic components. Dr. Garrou is an IEEE fellow and vice president of technology for IEEE's Components, Packaging and Manufacturing Technologies Society. He has served as president of IMAPS (1997), where he is a fellow and recipient of the 2000 William Ashman Award for advances in the field of microelectronic packaging.
Phone: 1-919-248-9261
Fax: 1-919-248-9265
e-mail: pegarrou@dow.com

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REFERENCES

1. P. Garrou, "Wafer Level Chip Scale Packaging: An Overview," IEEE Trans. Adv. Packaging, Vol. 23, 2000, p. 198.
   
2. Y. Tsukada, S. Tsuchida, Y. Nashimoto, "Surface Laminar Circuit and Flip Chip Attach Packaging," Proceedings Int. Microelectronics Conf., Yokohama, 1992, p. 252.
   
3. www.cyclotene.com
   
4. J. Wu, R. Pike, C.P. Wong, D.Scheck, W. Rogers, P. Garrou, "Evaluation of the Environmental Protection of Photo BCB Polymers," Proceed. Int. Symp. Adv. Packaging Materials, Atlanta, 2000, p. 90.
   
5. T. Kawahara, "Super CSP," IEEE Trans. Adv. Packaging, Vol. 23, 2000, p. 215.
   
6. A. Badihi et al, "A CSP Optoelectronic Package for Imaging and Light Detection Applications," Proc. IMAPS Conf., Tel Aviv, 1998, p. 1.
   
7. M. Toepper, J. Simon and H. Reichl "Redistribution Technology for Chip Scale Package Using Photo-BCB," Future Fab Int., 1996, p. 363.
   
8. M. Toepper et al, "Fab Integrated Packaging (FIP): A New Concept for High Reliability Wafer-Level Chip Size Packaging," Proceed. 50th Electronic Component Technology Conf., Las Vegas, 2000, p. 74.
   
9. N. Kelkar, R. Mathew, H. Takiar, L. Nguyen, "MicroSMD - A Wafer Lever Chip Scale Package," IEEE Trans. Adv. Packaging, Vol. 23, 2000, p. 227.
   

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