TED in Ultra-Shallow Implants: A Non-Issue?
Peter Singer, Editor-in-Chief -- Semiconductor International, 10/1/2000
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Today, it's not uncommon to address TED problems with multiple anneal steps. However, according to new research from Philips Semiconductors (San Jose, Calif.) and Varian Semiconductor Equipment Associates (Gloucester, Mass.), these extra steps are unnecessary for ultra-shallow implants, since TED effects are negligible. In a study focused on 0.15 µm CMOS technology, researchers found that additional anneal cycles "are of little benefit ... and that the shallowest junctions, and best device performance, can be obtained by eliminating extra annealing steps and using only a final anneal cycle after the source/drain implants."
In a report in the IEEE Electron Device Letters (Sept. 2000), the researchers say they believe the TED effects are minimal for this technology generation because the implant energies are so low. They note that the number of point defects created by an implant step is dependent on both the energy and dose; thus, low-energy implants will create fewer defects. More important, the implant damage will be created very close to the silicon surface. Point defects recombine at the silicon surface, so if the damage is confined to the surface most of the point defects will recombine quickly and not contribute to dopant diffusion. Also, as implant energies are lowered, the increased annihilation of the point defects at the silicon surface will reduce or even eliminate the formation of extended defects at the end of the range. Under most thermal processes, the dissolution of these extended defects is believed to be the main cause of TED.
For these reasons, the researchers -Jeffrey Lutze, Tony Miranda and Greg Scott of Philips; and Chris Olsen, Naushad Variam and Sandeep Mehta of Varian - say extra anneal steps designed to reduce TED problems are a waste of time. They specifically point to the rapid thermal anneal (RTA) step used after nitride spacer deposition as unwarranted. In theory, the furnace cycle from the nitride deposition allows the point defects from the implant damage to drive the junction deeper into the silicon, and the extra RTA step eliminates that problem. In reality, say the Philips/Varian team, the RTA step actually is driving the junction deeper than the TED effects from the spacer deposition - because there are no TED effects.
| Transistor Data for Various Process Options The nominal gate length is 0.15 µm and all tests are at a Vdd of 1.5 V and room temperature. (Source: Jeffrey Lutze, et al) | ||||||
| PMOS | NMOS | |||||
| Ext dose (cm-2) Ext RTA | 3x1014 Yes | 3x1014 No | 5x1014 No | 5x1014 Yes | 5x1014 No | 1x1015 No |
| Idsat (µA/µm) | 270 | 180 | 260 | 690 | 570 | 680 |
| Id0 (nA/µm) | 1.2 | 0.01 | 0.2 | 3.0 | 0.5 | 1.5 |
| Leff | 0.074 | 0.084 | 0.068 | 0.087 | 0.099 | 0.077 |
| Rseries (V-µm) | 800 | 820 | 740 | 180 | 200 | 120 |
| Vt (V) | 0.33 | 0.44 | 0.40 | 0.30 | 0.36 | 0.34 |
The devices used in the study were fabricated using shallow trench isolation, retrograde wells, a 3.3 nm gate dielectric and a nominal gate length of 0.15 µm. After gate patterning, the transistor was fabricated with shallow extension and angled pocket implants, in some cases followed by an extension RTA step. The transistor formation was completed with nitride spacer formation (LPCVD nitride deposited at 770°C for 110 min), deep source/drain (S/D) implants, S/D RTA and cobalt silicide formation steps. The short loop experiments used a process flow of: extension and pocket implants, extension RTA on some wafers, spacer deposition and RTA. All samples used a BF2 implant at 3 keV and a dose of 5 x 1014/cm2.
