Leaders Describe "Surmountable" Copper and Low-k Hurdles
-- Semiconductor International, 9/1/2000
More than 300 attendees gathered at Semiconductor International's 18th Annual SEMICON Breakfast for a discussion of the formidable, yet surmountable challenges associated with using copper interconnects and low-k dielectrics in damascene structures for the 0.13 µm processing era. Roundtable speakers included Mark Bohr of Intel Corp. (Portland, Ore.), James Ryan of IBM Microelectronics (Hopewell Junction, NY), Mong-Song Liang of TSMC (Hsinchu, Taiwan), Robert Havemann of International SEMATECH (Austin, Texas) and Gabe Kim of NEC Electronics (Roseville, Calif.)."The greatest inhibitor to copper processing is commitment," said Ryan, senior technical staff member and manager of interconnect technology at IBM. He explained that mastering the integration issues associated with copper and low-k dielectrics requires people to "adapt, improvise and overcome." He pointed out, "The execution of dual-damascene is difficult, not so much from a metalization standpoint but from a patterning standpoint." Ryan confirmed previous announcements of IBM's intention to offer 0.13 µm copper and low-k processing (with Dow Chemical's SiLK dielectric) in 2001, and added that low-k materials for a sub-2.2 effective k value must be available this year for possible integration at the 0.10 µm technology node. Desired qualities of a porous dielectric include a highly uniform and reproducible porosity, such as that demonstrated by the Dendriglass organic material with 4-12 nm pore size (Fig. 1).
Dr. Bohr, Intel fellow and director of process architecture and integration, compared copper with aluminum interconnect processing. "With aluminum, we have very good vertical dimensional control, but copper damascene processing offers degraded control due to trench etching and CMP components," he said.
In describing low-k dielectric challenges, Bohr highlighted the goal of reduced total interconnect line capacitance, the performance of which relies on selecting a low-k ILD with sufficient mechanical strength and integration capability, and combining it with very thin etch-stop layers, also having low dielectric constant. In the face of increasingly difficult integration, increasing number of process steps per layer and the 300 mm conversion, Bohr further emphasized the economic challenges of containing interconnect processing cost, which now accounts for 50% of wafer processing cost.
Dr. Liang, senior director of R&D Advanced Module Technology Division at TSMC, announced his company will first run copper and low-k processes on 200 mm this year. In the first quarter, 2001, TSMC will run 200 mm wafers with aluminum and copper interconnects and a 300 mm copper pilot line, moving to copper/low-k 300 mm processing six months later. He summarized the barriers associated with bringing copper into manufacturing (see Table) with an emphasis on faster learning, process control and production management. Dr. Liang added that copper damascene technology poses issues of mechanical integrity of the film stack and the need for in situ resist, liner dielectric and polymer removal for via contact resistivity control. Other issues he pointed out included pattern sensitivity of copper CMP, which causes dishing of the copper feature and erosion of the underlying nitride, the importance of low-k dielectric thermal stability, and the possibility of electromigration with some low-k materials and in certain interconnect geometries.
| Table. Barriers in Manufacturing Copper Interconnects | |
| Strategy | Issues |
| Design rule and chip architecture | Must match with metal/dielectric film stacks to take full advantage of copper/low-k dielectric interconnect. |
| Contamination control | Facilities (DI water, air, exhaust, etc.)and accessory isolation required. Prevent production floor management from impacting tool utilization efficiency. |
| Monitoring procedures | New materials such as electrolyte,slurry and spin-on dielectrics. Process controls of CMP endpoint and effects on pattern density are essential. |
| In-line metrology | Via polymer detection, ECP grain distribution and post-CMP thickness monitoring. |
| Defect inspection | Inspect copper ECP voids, CMP corrosion/scratches/pitting. |
| Evolving materials and tools | Can create gaps between development and mass production technologies. |
| Yield/CoO | Rapid manufacturing learning required. |
| (Source: M.S. Liang, TSMC) | |
Dr. Havemann, a TI fellow currently on assignment to SEMATECH as program manager for copper/low-k integration, presented the likely material changes in going from today's 0.18µm processes to 0.13 µm in 2002, 0.10 µm in 2005 and 70 nm in 2008. The changes reflect the need to reduce overall capacitance (by going to a lower dielectric constant, k) and to fill increasingly higher-aspect-ratio dual-damascene structures with the copper barrier and seed layers before depositing the bulk wire.
Today's processes use an oxide or FSG interlevel dielectric, a PVD Ta/TaN barrier, copper PVD seed layer and electroplated copper fill. At 0.13 µm, OSG or organic ILDs (keff = 3.5-2.7) will replace oxide, the Ta/TaN barrier will be deposited by ionized PVD or CVD processes and the copper processes will remain unchanged. At 0.10 µm, porous dielectrics may come into play (keff = 2.2-1.6), CVD of the Ta/TaN is likely for adequate step coverage and to prevent voiding, and CVD copper seed and electroplating are likely.
At the 70 nm generation, a keff value of 1.5 is desired, using very porous films or an air gap; ideally the copper barrier thickness goes to zero; and a lower-resistivity copper interconnect, possibly deposited by CVD for seed and fill, is needed. "At these device geometries, 500 Å of copper CVD will fill the structure," explained Havemann. However, he noted, "This presents a huge question because, so far, the reliability of the structure using CVD copper is not very good." At the 70 nm node the Roadmap indicates the copper interconnect needs to deliver an effective conductor resistivity of 1.8 µW-cm, down from today's value of 2.2 µW-cm. He added that the grain size of copper is not well controlled and is a function of geometry. "Of course, you want the lower resistivity associated with larger grains, but in small features you tend to get smaller grains," he said.
|
|
Havemann and Bohr both discussed the necessary three-dimensional CD control for copper damascene processing, since structures typically contain variations in metal thickness and spacing at different metal levels of the device. Havemann highlighted the need for very selective CMP and etch processes, excellent etch profile control, and preventing CMP erosion that affects the resistance of the lead and sidewall capacitance. Summarizing the integration issues (Fig. 2), he added that in multilevel interconnects, the poor thermal conductivity of low-k dielectrics can cause the upper leads to get very hot, inducing electromigration. Since both wire bonding and flip-chip packaging are needed across many companies' product lines, some low-k dielectrics may require the use of supporting oxide layers or other methods to ensure the chip can endure the force of wire bonding.
Finally, Dr. Kim, associate vice president of operations of NEC Electronics' Roseville, Calif., facility, outlined the company's roadmap for advanced devices. The strategy will include the introduction of a 300 mm wafer pilot line in Hiroshima, Japan, in 2002, coincident with the manufacture of 256 Mb DRAMs, a 0.13 µm process. The fab is estimated to cost $1.4B and eventually will produce 25,000 wafers/month (300 mm).
The panelists provided words of advice to equipment and materials suppliers: identify specific joint development projects at the early stages of development; respect individual intellectual property, and develop long-term mutual trust; and introduce materials and processes well ahead of roadmap targets so complex integration challenges can be overcome. •
— Laura Peters
