Thermal Mapping Speeds DUV Resist Evaluation
Leo Sharkey, Sean LeBlanc and Steve Keledjian
Shipley Co., Marlborough, Mass. -- Semiconductor International, 9/1/2000
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At a Glance | | |
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CA resist processing
Integral to the function of chemically amplified resists is thermal processing: these resists rely on a heating cycle after exposure to activate and a subsequent chill step to quench a chemical reaction that enhances exposure sensitivity.1 Temperature variation during this bake step directly affects the dimensions of the exposed pattern. Pattern control is characterized and monitored by measuring a critical dimension (CD) that usually is the smallest dimension that needs to be precisely resolved.
During CA resist processing, the wafers are baked immediately after resist application (the post-apply bake, or PAB) and again after exposure (post-exposure bake, or PEB). The post-exposure bake is the more critical step since it activates the chemical reactions that catalyze the amplification of the initial UV-light-induced latent image. Within-wafer or between-wafer temperature variations during post-exposure bake (and also sometimes during post-apply bake for resists that have a lower activation energy) will contribute significantly to linewidth variation. Chemically amplified resists currently under study differ widely in thermal sensitivity; two examples are listed in the Table.
| Table. Post-Exposure Bake Thermal Sensitivity of DUV Photoresists | ||
| Resist | Exposure wavelength | CD sensitivity (nm/°C)(nm) |
| Shipley APEX E2 | 248 | 16.0 |
| IBM Version 1B3 | 193 | 3.8 |
Thermal variation during resist processing is one of many sources that contribute to the total CD variation, and it is important to be able to separate the various causes of variation during process optimization and troubleshooting. For chemically amplified resist evaluation, it is important to be able to actually eliminate thermal variation as a significant source of CD variation.
Wafer temperature variation
In the typical bake plate in a production lithography wafer track, a closed-loop controller maintains temperature by varying the power to a single heating zone, based on the feedback from a single temperature sensor in the bake plate. The chill plate is cooled and maintained near ambient temperature by circulating a controlled-temperature fluid through channels near the surface of the plate. Thermoelectric cooling also can be used to improve recovery from the thermal transients induced by the hot wafer.
No matter how accurate the temperature control of the hot and chill plates, it is the temperature of the wafer and the resist coating that really matters. Wafer temperature can differ substantially from plate temperature. To minimize backside contamination, wafers are not placed in direct contact with the plate, and heat transfer between the plate and wafer is by conduction through a thin (typically 50 to 150 µm) stagnant layer of gas. In proximity mode baking, conductive heat transfer is the predominant heating mechanism, while conduction and convection above the wafer are the primary means of heat loss. As a result, the wafer temperature is influenced by several variables, such as bake plate temperature uniformity, wafer position on the bake plate, the temperature of the bake chamber wall and cover, and the purge/exhaust gas flow velocities and flow patterns above the wafer. Other factors include bake plate cover sealing efficiency, bake plate thermal inertia, and contamination on the bake plate surface or on the wafer backside.
The single temperature reading from the resist track bake plate controller is not adequate for optimizing bake plate temperature variation. Only one temperature sensor is in contact with the bake plate, and the bake plate itself can have more than one heater and temperature zone. As previously mentioned, heater malfunction, exhaust non-uniformity and other factors can cause temperature variation across the bake plate and wafer. The temperature of the wafer itself must be measured in situ with sufficient precision and with both spatial and temporal resolution. When the wafer temperature profile is known accurately, the effects of various heating and cooling parameters on the resist can be assessed and optimized using resist thickness variation or linewidth variation as the metric.
Data in the form of a wafer temperature map versus time can be used to:
•Characterize bake plate temperature uniformity (select the best plates for the critical post-exposure bake step).
•Identify faulty bake plates and controllers, and make adjustments as required.
•Match processing temperatures for multiple bake plates.
•Pinpoint temperature non-uniformity that is due to non-uniform exhaust or nitrogen purge flow.
•Quantify and control thermal sensitivity to wafer-centering on the bake plate.
•Locate and correct any wafer-to-bake plate proximity gap non-uniformity.
If we directly measure wafer temperature in situ on both hot and chill plates, the information gained can be applied to reduce, and even reduce to insignificance, the effects of thermal variation on resist performance. For example, if an exposed wafer could receive its post-exposure bake on any one of several bake plates, then all the bake plates assigned to perform the post-exposure bake step could be matched in temperature. In situ temperature measurements also can be used to identify and correct variance due to bake plate non-uniformity. If temperature profile maps of the bake plates are available, the most uniform bake plates can be selected for the critical post-exposure bake.
Temperature profile data also can be used for troubleshooting and correcting conditions such as purge flow anomalies that cause resist bake temperature non-uniformity. In one case, thermal mapping showed thermal variation could not be a cause of an anomalous thickness variation. A single-point thermal measurement would not have given such a clear-cut diagnosis.
Choice of metrology
There are two ways to evaluate wafer temperature variability: test wafers (indirect) or in situ measurements (direct).
The lithography process itself — that is, the critical dimension achieved — can be used to infer the post-exposure bake temperature. In this approach, wafers are processed at various post-exposure bake temperatures, the resulting CDs measured, and the relationship between the CDs and temperature set point of the post-exposure bake plate determined. (All other parameters are held constant). Thereafter, within-wafer temperature uniformity can be inferred by comparing CDs within the wafer.
Processing test wafers and measuring the resulting CD always will be an important technique for final photoresist evaluation and process verification. But this method of in situ metrology has several drawbacks. For each area tested on the wafer, a single data point is provided that is the integral of a thermal and process history that is influenced by many factors. The missing parameter is the thermal history. The wafer temperature varies during the heating cycle, and it is not possible to determine the temperature versus time profile. This limits the ability to properly characterize the resist. Other disadvantages of CD test wafers include a limited temperature range and one-time use, after which the wafers must be cleaned, recoated with resist and processed. The use of CD test wafers to evaluate and set process parameters is costly in terms of wafers, resist and stepper/SEM time consumed.
A simpler, but less sensitive, way to evaluate thermal variation is to measure the variation in resist thickness after thermal processing. This method requires only coat, post-exposure bake and thickness measurement, and avoids time-consuming stepper wafer processing and SEM CD measurements.
Direct measurement with instrumented wafers
We have evaluated an instrumented wafer thermal metrology method from SensArray Corp. (Santa Clara, Calif.). It includes a data acquisition and display system4 and instrumented wafers with either 9-point or 17-point embedded resistance temperature detector (RTD) arrays.5 The RTD calibrations are NIST-traceable and accurate within the DUV post-exposure bake temperature range.
The first task was to match four bake plates at 130°C.6 This was done by making an approximate adjustment to the proportional integral derivative (PID) temperature controller of each bake plate based on the mean of a single measurement from a 9-point embedded-RTD wafer.
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Once the bake plates were within a workable range of their target temperature, each bake plate was profiled with a 17-point RTD wafer and precisely matched.
With the track in maintenance mode, the instrumented wafer is centered on the first bake plate to be matched, and the bake plate cover is closed against the flat cable connected to the sensors. The purge or exhaust flow is adjusted to its normal level. The data display is configured to show mean temperature, and the data acquisition is started.
The wafers were profiled over a five-minute interval at a sampling rate of once per second. The acquisition display is monitored in real time to determine when wafer temperature has stabilized, and the mean temperature value of the wafer is noted. All data taken during the test can be saved to a file. It takes 10 to 15 minutes to measure the mean temperature for one bake plate. The mean values for these data were used to determine the proper offsets for each plate.
The new offsets were implemented, and the plates were allowed to equilibrate for 24 hours. Then the plates were re-measured following the same procedure as the initial measurements. These data were analyzed for stability and cross-wafer uniformity. Small adjustments were made to second-order derivatives for each PID controller. This fine-tunes the temperature controller and further reduces the small amount of initial temperature cycling that occurs after the wafer contacts the bake plate.
The matching procedure normally can be accomplished in an hour or less (plus the bake plate temperature stabilization time). To accomplish the same task using test wafers would require several hours, not including the time and cost of lithography processing and CD measurements on 45 (or more) wafers. Bake plate matching using instrumented wafers also is more certain because the temperature measurement is direct and not a temperature inferred from changes in CD or resist thickness.
The data were exported to a spreadsheet format and analyzed for non-random and cyclic patterns. Based on the thermal map data, the temperature settings for each plate could be adjusted to minimize thermal excursions as the bake plate lid opened and closed.
Thickness test matrix
The next step was to run thickness test wafers to determine the variation of the photoresist thickness for a constant post-exposure bake plate temperature.7 Two coaters (C1 and C2) were used, and each test run consisted of 25 wafers per coat bowl. Test runs were conducted on five days over a 12-day period. Each 25-wafer run was sent through four different bake plates in a random order. A minimum of 60 wafers was baked through each bake plate, and 49 points were measured on each wafer. The results are shown in Figure 1.
These data indicate that a very stable process was achieved by carefully matching the bake plate temperatures. (Note: The high thickness and sigma points for Day 8 were traced to a problem with the resist dispense pump that was shared by both coaters.)
Stability test
After the bake plates were matched, a stability test was performed to assess measurement repeatability. One bake plate was set at 108°C, and six measurements were made one-half hour apart over a period of 2.5 hours. Each measurement was for five minutes, sampling once per second. The data then were exported and analyzed using the integrated data acquisition and mapping system. Typical measurement data for repeatability over a 2.5-hour interval are shown in Figure 2.
Effect of exhaust flow
We suspected exhaust flow variations were affecting bake plate temperature uniformity on one particular coater track. A 17-point RTD wafer was placed in the bake plate chamber. Three levels of exhaust velocity were introduced to the track: 310, 1030 and 1300 linear ft/min as measured by a 2 in. diameter anemometer. The bake plate setpoint was 135°C. The wafer temperature was allowed to stabilize for five minutes prior to the temperature measurement, and three measurements were made at each exhaust level. The order of exhaust levels was randomized. The exhaust level was then compared to the measured wafer mean temperature and standard deviation. These data are plotted in Figure 3. Higher velocities decrease the mean temperature, but a moderate velocity resulted in the best uniformity (lowest standard deviation). As a result, variation in exhaust velocity was ruled out as a significant cause of the bake non-uniformity exhibited by this track.
Conclusion
Using the data analysis system, bake plate temperatures can be calibrated with a single test run. The ability to measure wafer temperature and optimize the temperature controllers within a fraction of a degree C makes this measurement technique indispensable for DUV photoresist evaluation and processing. Use of the instrumented wafers and data analysis system improved the quality of thermal controls and reduced the overall cycle time required to calibrate, test and accept a new photoresist-processing track. It is possible to set up the track so bake plate temperature variations have no measurable effect on the resist thickness or final CD. This effectively eliminates thermal effects as relevant parameters during resist evaluation testing.
Once a track is qualified, the thermal mapping technique should prove useful as a process maintenance and troubleshooting tool. The best strategy for dealing with thermal effects is to find them before your process does. Once the lithography process is optimized, regular preventive maintenance can keep it qualified. Early detection of temperature drift and non-uniformity enables fixing temperature-related problems before they cause expensive downtime and yield loss.
Direct substrate temperature measurement using temperature-sensor instrumented wafers and data acquisition and analysis systems provides both spatial and temporal resolution, and meets the precision requirements of DUV lithography processes. CD uniformity problems can be traced rapidly to their root cause without the resource-intensive processing of CD test wafers. •
Leo Sharkey is manager of cleanroom systems engineering at Shipley Co., where he has worked since 1998. He previously worked for IBM Microelectronics Division (Essex Junction, Vt.) as lead engineer for the i-line track process group. He has a B.S. in chemistry from the University of Michigan (Ann Arbor) and an M.S. in mechanical engineering from Ohio State University (Columbus).
Sean LaBlanc is senior process technician at Shipley. He has worked at Shipley for six years: three as a chemical operator and in the manufacturing group, and three as a process technician in cleanroom systems engineering.
Steve Keledjian is a process/equipment engineer at Shipley. He previously worked for MKQC (Shrewsbury, Mass.), a joint venture between Quantum and Matsushita, as metrology/process engineer. He has a B.S.E.E. from Northeastern University.
REFERENCES
- D. Seeger, "Chemically Amplified Resists for Advanced Lithography: Road to Success or Detour?" Solid State Technology, 40(6), pp. 115-121 (June 1997).
- M.A. Zuniga, N.N. Rau, A.R. Neureuther, "Advances in Resist Technology and Processing," SPIE Proceedings, Vol. 3049 (1997), pp 256-268.
- R.R. Kunz, R.D. Allen, W.D. Hinsberg and G.M. Wallraff, "Advances in Resist Technology and Processing," SPIE Proceedings, Vol. 1925 (1993), pp. 167-175.
- "Temperature Metrology for CD Control in DUV Lithography," Jeffrey Parker and Wayne Renken, Semiconductor International, Sept. 1997, pp. 111-116.
- SensArray 150 mm wafer. Part No. 1840A-6-5024. SensArray Corp., Santa Clara, CA.
- The bake plates were in an FSI Polaris 2200 Micro Lithography cluster.
- Shipley UVIII-0.5 photoresist was used. Resist thicknesses were measured with a ThermaWave OP5240 DUVSE measurement tool.
The authors thank Paul Buccheri and Dr. Charles Szmanda.
