Why Silicon-on-Insulator?
M.J. Reid, Ibis Technology, Danvers, Mass. -- Semiconductor International, 8/1/2000
The idea of insulating the thin semiconductor layer where transistors operate from an underlying substrate has been around for years, used in rf, high-voltage, high-temperature and radiation-tolerant electronics. Reducing the coupling between circuits and supporting substrates cuts power consumption and noise, and, most importantly, allows higher-speed IC operation.Now, silicon CMOS is starting to use silicon-on-insulator (SOI). Without SOI, today's leading CMOS microprocessors are reaching speeds in excess of 700 MHz, mainly due to device scaling to < 0.25 µm. CMOS, however, continues to scale to smaller feature sizes (<0.15 µm), larger transistor counts and lower supply voltages. Achieving higher operating frequencies (>1GHz) and controlling power consumption are becoming more challenging and providing competitive advantages to those who do it the best. This is why SOI is now making significant inroads with CMOS. Using CMOS on SOI, several major IC manufacturers have demonstrated that wafers with a thin (<0.2 µm) layer of high-quality silicon, insulated from the silicon substrate by a thin (<0.4 µm) layer of silicon dioxide buried below the wafer surface, display speed improvements of 25%-35%. At the same time, SOI circuits have demonstrated significantly reduced power consumption, operation to lower supply voltages and improved soft-error immunity over non-SOI counterparts.
To continue to increase performance and keep up with Moore's Law, companies have adopted several cumulative approaches, including continued shrinking of bulk CMOS devices, using copper wiring and using low-k/high-k dielectrics. In each case, a change is made to the existing leading-edge silicon-wafer-based CMOS process, as is the case with adoption of the thin SOI wafer. Ghavam Shahidi of the IBM Research and Development Center recently said, "SOI may be more important than copper for staying on the technology Roadmap."
The SOI wafer is essentially the same as the bulk or epitaxial wafers used for silicon bipolar and CMOS technologies. A type of SOI wafer, called thick SOI (for the relatively thick silicon and buried oxide layers of >1 µm), has been used in military and some commercial bipolar and BiCMOS circuit applications, including high-voltage and high-power devices. This IC market segment, at perhaps $50M/year, is a small piece of the $110B commercial, mainstream CMOS integrated circuit market.
Radiation-hardened CMOS devices have been using thin SOI for several years. Over the past few years, scientists and manufacturers have invested significant work to further develop thin SOI wafers and processes to provide the types of benefits for commercial CMOS circuits that other wafers have provided for rf circuits. But these SOI wafers also must provide a migration path from existing silicon-based CMOS processes, including scalability to 300 mm. The net result is economically compelling: the wafers must meet the same high-quality standards of 200 mm and 300 mm wafers used in today's fabs, while remaining economical for manufacture. The industry has pursued two primary methods for making these wafers: implantation of oxygen (SIMOX) and the bonding of two wafers followed by removal of one of the wafers (bonded wafers).
In the past 18 months, SOI has gained recognition as a critical step in continued improvement of CMOS circuit performance. After years of work, SIMOX-SOI wafer and device fabrication processes have achieved sufficiently high quality and low cost to be applied commercially. In August 1998, IBM announced it would apply its leading-edge CMOS technology, including copper interconnects, to commercialize SOI CMOS products based on SIMOX. The company believes SOI processors are 30% faster than bulk CMOS versions, provide comparable circuit yields and add less than 10% to wafer processing cost. Other companies also have announced transition to SOI for high-speed microprocessors or low-power logic circuits.
IBM has said recent advances in SIMOX-SOI wafer production will cut incremental processing costs of SOI to only 3%-5% over the cost of the bulk versions. This is clearly much less than the overall cost of any other insulating or semi-insulating wafer technology approach. Recently, other companies have entered the SOI wafer fabrication or related infrastructure (such as SOI circuit design CAD tools or SOI metrology) markets. This is a positive development, supporting IBM's claim that virtually all CMOS could move to SOI in the next few years. It appears that with all-CMOS ICs as the potential market, thin SIMOX-SOI will not remain simply a niche technology.
