IMEC Takes System-Level Approach to DFM

At the 65 nm node, something new starts to happen to manufacturing tolerances. They stop scaling with physical gate length of the transistor and begin to significantly increase the variability of the device characteristics, negatively impacting chip yield. Another new phenomenon at 65 nm is thermal differences from one die to another on a wafer; dynamic variability at run time that narrows the operating window of the circuits. This amounts to smaller operating windows for electronic systems, and IMEC (Leuven, Belgium) believes only a system-level approach will be sufficient to address these problems in the future.

Bringing together electronic design automation (EDA) providers, integrated device manufacturers and tool vendors in its latest industrial affiliation program on system-level integration (SLI), IMEC aims to develop solutions for the rapidly increasing number of design-for-manufacturing (DFM) problems the industry is encountering.

The SLI program is also designed to address two primary problems: device power consumption and current leakage, according to Rudy Lauwereins, vice president of design technology for Integrated Information and Communications Systems at IMEC. Power consumption increases significantly because of thermal heating, rapidly increasing static leakage and increasing energy in the interconnects. Increasing interconnect delay leads to timing closure problems. The main performance metrics of the program are energy, delay and area.

IMEC is focusing in on low-power ICs used for wireless and multimedia applications. The variability of concern is at the die level (intra-die), which need to be controlled and predicted. "With these parametric variations, it is almost like analog behavior in digital circuits," said Karen Maex, IMEC fellow. The causes of mismatches between one device and another can be stochastic in nature, such as doping level fluctuations, line-edge roughness or boron penetration, for instance. Or they can be systematic, caused by changes in temperature or stress. The program will determine trade-offs between speed, power, accuracy and yield.

Maex made it clear that the research consortium's aim is not to develop a software package. The goal is to create the tools and methodologies in-house that are needed to design power-aware systems. "Once we can do that in a reliable way for structures and systems, continually verifying our work in silicon, we can use it as a productive tool to evaluate, for instance, how nanotechnology is going to help us, or in what context optical interconnects will be useful." She added, "When you have to make a decision about a technology improvement, and you're going to dedicate your research resources, it's better to know what it's going to buy you."

Because advanced wireless systems are data-dominated, memories account for a dominant portion of energy consumption and chip area. Therefore, the program will focus on providing adequate system design methods and tools for exploring and optimizing memory architecture, memory organization and memory interconnection on a system-on-a-chip (SoC). IMEC has chosen embedded SRAM as its test vehicle. One method by which performance could be improved uses buffers on the array periphery, which act as "Pareto configuration knobs," dynamically adjusting leakage and power consumption of the SRAM, with little expense due to their small footprint. For instance, at the 65 nm node, a 10% variation in threshold voltage (V_t) leads to 40% variation in access time for a 1 kB memory. Sigma-based design leads to low yield and overhead. But with IMEC's concept of 100% yield with variation toleration, you "just live with the speed you get, and for those data points falling outside the spec, variable amplification in the buffer is used to switch to a different/faster implementation, using an additional driver step," Lauwereins said. IMEC has developed two embedded SRAMs, each with two configurations to address process variations depending on whether or not the application calls for low energy or high performance. Another strategy powers down the word lines not in use.

IMEC's framework will enable users to concurrently explore the impact of technology scaling, and static and dynamic variability on circuit and system performance for various architectures. EDA and IC manufacturers will be able to identify main technology limitations and how to overcome them via novel design methods. It will also allow equipment makers the means to benchmark the potential of a given improvement in manufacturing tolerance on device variability, circuit and system performance. These are capabilities the industry has never had at its disposal.