New Hope for Ultralow-k Integration

The semiconductor industry is keen to reduce RC time delays, and one of the most effective ways to do that is to move to dielectrics with lower dielectric constants. SiO₂ has a k value of 4.1, fluorinated silicate glass has a k value of 3.1 and newer carbon-doped oxides have a k value of 2.9-3.0. Most 65 nm interconnect technologies announced to date employ carbon-doped oxides, but there is a huge performance benefit in going to even lower k values. The International Technology Roadmap for Semiconductors (ITRS) has a target for effective k values (k_eff) of 2.3-2.6 for the 45 nm node, 2.0-2.4 for the 32 nm node and <2.0 for the 22 nm node (k_eff is defined as the k value after the materials are integrated/processed). The lowest k value achievable is 1.0, which is that of air.

The main problem in going to low-k dielectrics with a k value of 2.3 and below, which many define as ultralow-k or extreme low-k, is that the materials are porous (so they incorporate more air) and generally considered "fragile" in that they have low mechanical strength. These properties lead to integration challenges, meaning they may require capping and pore-sealing layers.

However, recent work at IBM (White Plains, N.Y.), scheduled to be presented at next month's International Electron Devices Meeting (IEDM) in San Francisco (Dec. 13-15), shows that it's possible to achieve a k_eff of 2.1 using what is actually a fairly old process technology: etchback and gap fill. In fact, the researchers say that the holy grail of k=1.6 is achievable with this technology with "limited modification to the existing dense IMD (intermetal dielectric) fabrication infrastructure."

1. The etchback, gap-fill process flow removes conventional dielectric in a dual-damascene structure and replaces it with a porous low-k dielectric. The advantage of the process is the low-k material is deposited only after most processing steps are completed, avoiding many integration problems.

Although this may require some improvements in CMP technology to minimize dishing of the low-k dielectric, the IBM researchers say there are four primary advantages of the etchback, gap-fill approach. In an abstract provided by IEDM conference organizers, they state the advantages as:

• The porous IMD material is not exposed directly to any resist strip plasma.
• The liner and seed materials are deposited on a dense dielectric, and thus there is no opportunity for any potential diffusion of these materials into porous IMDs.
• The dense support dielectric material underneath the metal lines provides mechanical reinforcement with a minimal increase in the overall capacitance of the BEOL interconnect.
• The pore size control of the gap-fill IMD is not as critical for this scheme as it is for conventional dual-damascene integration since the porous low-k material is introduced after the formation of the dual-damascene interconnect wires. However, in this scheme it is necessary for the IMD to be able to fill very narrow gaps with high aspect ratio (4:1) and withstand direct CMP planarization.

New CMP processes were developed to prevent the degradation and dishing of the porous IMD materials used in this integration scheme. These materials typically have porosities in the range of 40-55 volume percent. Figure 2 shows dense and isolated patterns where dishing is minimized.

2. A post-CMP image of a dense array of lines (left) and an isolated line (right) with the gap-fill low-k dielectric. A dielectric CMP was developed to minimize dishing.

For additional information on wafer processing, go to www.semiconductor.net/wafer