Creating Stable and Flexible Chips for Thin Packages

Wafer thinning has become a key technology for the semiconductor industry during recent years. It has facilitated such technologies as smart cards and RFID devices, and is becoming a significant enabler for the stacked-die packages that are increasingly prevalent in the latest cell phones, PDAs and other smaller, lighter, more powerful electronic devices.
 
As wafers are thinned to <100 µm, manufacturers must incorporate new methods of thinning beyond mechanical backgrinding, and they must be more concerned about such parameters as the wafer's breaking strength, flexibility, roughness and dicing quality. This article will detail findings of the mechanical properties of wafers after thinning, and discuss which parameters are the most important for viable thin packages.

From a material point of view, silicon is quite stable, but brittle, so that silicon wafers show a certain amount of fragility. During the wafer thinning process, in particular, wafers are stressed mechanically. Stability at the wafer level is a key factor in wafer breakage. But for back-end processes and product applications, it is the stability at the chip level that is the most critical.

There are several products in which the chips need a breaking strength, or flexibility, such as smart cards and other similar applications. There are two main aspects of this — the mechanical properties of the chip, and the mechanical properties of the package — and each influences the other. This paper focuses on the mechanical aspects of silicon chips.

There are many ways to measure chip strength, and it is difficult to compare results from different measuring systems. There is really no right or wrong method, but you must keep in mind which system you are using. Mainly, we want to check the breaking strengths resulting from different process flows during the wafer thinning process. Our preferred method is the ball-ring method; another common technique is three-points bending.

In the ball-ring method (Fig. 1 ), a ball is pressed down on a chip, moving forward slowly at 1 mm/min. Force and movement are measured continuously until the chip cracks. This method is less influenced by the dicing quality, because the chip edges are far enough away from the ring.

1. The ball-ring method of measuring breaking strength presses a ball onto a chip, moving forward slowly. Force and movement are measured continuously until the chip cracks.

Sometimes we also do a three-points bending test (Fig. 2 ), because this more closely resembles the stress the chip would see in real-world applications. For some applications, flexibility is the most important feature of a chip, but there are other parameters that will influence the failure or success of a chip in field applications. In this method, the third rod is pressed down on a chip. Speed is again measured at 1 mm/min, which is similar to the ball-ring method. The system is controlled by a PC, which is continuously storing data for every chip of the lot.

2. A three-points bending test is more similar to the stress a chip will see in the field. Here, a rod is pressed onto a chip, again moving forward slowly. Measurement is similar to the ball-ring method.

As mentioned previously, silicon is a very brittle material. It is known that the distribution for breaking strength is asymmetrical relative to the average force. The most common distribution used in diagrams is a Weibull distribution (Fig. 3 ): the probability of breaking against breaking strength (in double logarithmic scale). We use F_average (arithmetric average) and sometimes F_median (force where 63.2% of the chips have cracked) to give a bit more information about the distribution.

3. The distribution of breaking strength is asymmetrical relative to the average force. The most common distribution is a Weibull distribution.

It is important to know what stress an application will likely induce. A credit card, for example, must be able to perform its function for several years, and must cope with the forces coming from daily use. A luggage tag, on the other hand, must function only for several days. The chip size is also a factor: a chip measuring 0.8 × 0.9 mm will not see much stress if, for example, the luggage tag is being bent. If you put a finger-tip chip on a credit card, it must sustain the bending force typical of a credit card. So here you need a certain stability and flexibility.

We think that flexibility is the more important feature. The force it takes to bend a smart card is a very common occurrence. The forces applied in your jacket or in your pockets are always higher than the breaking strength of the chip. The only option, therefore, is to have flexible chips.

In most cases, the breaking strength of the active side is quite high — nearly as high as that of an untreated frontside. This is why the main aspect of chip stability comes down to the backside treatment. Therefore, we often are unable to attain a threshold. More strength is better. What is the highest amount of breaking strength attainable in a chip? To answer this question, we first must look at the breaking strength attained with different wafer thicknesses.

To show chip breaking strength relative to wafer thickness, we performed experiments using 6 in. wafers with an original thickness of 675 µm. We measured breaking strength using both the ball-ring method (Fig. 4a) and the three-points bending method (Fig. 4b ), which produced similar results.

4. Both the ball-ring method (left) and three-points bending (right) show a significant loss of breaking strength after removing even a small amount of silicon from the wafer backside.

Two main aspects of the results are worth stressing:

1. By taking off 7% of the original thickness, we lose more than 60% in breaking strength. It is not only the thickness that decides breaking strength; the most decisive influence comes from the backside treatment.
2. Given a chip with a ground backside, the breaking strength is significantly decreased with reduction of thickness. If we reduce thickness by 30% (188 µm), strength is reduced to 4-7%.

The stability of the backside of the chip is the most decisive parameter we investigated, looking at various backside treatments and comparing those values to chip stability. In these investigations, we used the following process sequence: rough grinding — fine grinding — stress release — dicing. (Note: There are several different processes that can be applied for stress release.)

Figure 5 shows a comparison of various backside treatments and their resulting breaking strength. Looking at the 10 µm spin etch as a reference, similar strengths can be reached by chemical mechanical polishing (CMP) and plasma etch techniques. CMP shows further potential, but the highest breaking strength is achieved with the 25 µm spin etch process. We know that there is no point in further increasing this removal amount, and at this point the breaking strength shows saturation. The exact value sufficient for reaching saturation also depends on the grinding process used.

5. The highest breaking strength is shown with the 25 µm spin etch treatment.

Wet chemical etching is one of the most common thinning techniques. Spin etching, where an etching agent is supplied as a thin film on the surface of the rotating wafer, can be used to etch one side of the wafer. The front side of the wafer is protected by using a special chuck that allows the processing without surface protection layers or tapes. Typically, the chuck is designed to hold the wafer by vacuum to allow handling of ultrathin wafers.

Etching agents for silicon are made up of an oxidizing agent such as HNO₃ or H₂O₂; and a complexing agent, typically HF. The different mixtures allow different etching rates, and are characterized by different selectivities to layers with different dopant levels (e.g., epi layers) or silicon oxide. A typical value for the etching rate for spin etching of silicon is about 10 µm/min. The total thickness variation (TTV) value obtained for silicon etching is a function of the flow of the etching agent across the wafer surface. The latter can be optimized by parameters such as wafer rotation and swivel motion of the medium dispenser over the surface.

Spin etch, performed with an SEZ tool, can be used for two substantially different processes:

1. Bow and damage etch —To reduce wafer warpage, it is enough to remove several microns to increase stability; we find saturation latest at 25 µm.
2. Bulk removal —Here we use the spin etch as a thinning tool to avoid abrasive grinding at low thickness, which reduces the risk of wafer breakage. Instead of grinding to 50 µm, you could grind to 100 µm and do a 50 µm bulk etch. As the chip stability is already saturated, it is possible to vary the removal amount without changing characteristics such as chip stability or surface roughness. This can be used to control the end thickness. By aiming at a target thickness, the spin etch removal rate can be adapted to reach the intended end thickness.

We also measured backside surface roughness and compared this parameter to breaking strength. There is certainly a correlation between roughness and breaking strength (although we also found that the smoothest mirror surface does not necessarily lead to the highest breaking strength). For die bonding, backside roughness also influences the distribution of glue and the resulting adhesion. As a measure for roughness, we use average roughness (R_a) within a measuring distance of a few millimeters.

The most powerful tool in comparing the roughness of a wafer backside is often the naked eye. Down to an R_a of 0.1 µm, roughness is measurable by simple mechanical systems using a contact needle. Beyond this point, an optical measuring system or an atomic force microscope (AFM) is needed.

One of the most striking improvements in breaking strength is between rough grinding (often done with 300-400 mesh, the first step of the grinding process) and fine grinding (often done with 1000-2000 mesh, the second step of the grinding process). As shown in Figure 6 , taking off 20 µm by fine grinding results in a decisive increase of breaking strength.

6.Taking off 20 µm by fine grinding rather than coarse results in a significant increase in breaking strength.

The high removal rate, especially by the first grinding step (rough grinding), causes rough surfaces. Typical values are about 0.2 µm (R_a). During the second grinding step, the roughness is reduced to a few nanometers (e.g., using a wheel with mesh size 2000, roughness is reduced to an R_a of 10 nm, which is about 10× larger than for a polished bare silicon wafer). The roughness of spin etched silicon surfaces is <1 nm (R_a) and, therefore, almost comparable to CMP processes.

To remove 20 µm by fine grinding from a rough-ground wafer improves the breaking strength by a factor of two. This can be explained through a typical Hadamovsky model, which shows subsurface damage of 10-25 µm for any chip thickness. For a thinner chip, this subsurface damage is of course a more significant factor, because the damage layer is higher in relation to the overall thickness.

Separating dicing processes — dividing the wafer into chips — are decisive for the quality of the chip edges. The influence of edge quality on the breaking strength of chips is increasing as chips get thinner. Here, the separating-by-thinning technologies can gain advantage over the classic thinning and dicing. We will explain the reason and give an estimation on this correlation.

When considering dicing with respect to breaking strength, the main topic of interest is chipping, especially backside chipping. The tiny little pieces of silicon breaking off the edge of the chip during separation is called chipping. This effect is surely related to dicing quality, but some chipping cannot be avoided because dicing is a mechanical sawing process. The depths of these little damages, sometimes called "shell cracks," are a few microns. For chips thicker than 200 µm, it is difficult to find any change in breaking strength related to dicing quality if the separation is done after thinning.

The thinner the chips, the more difficult the breaking strength tests. It is difficult to handle these thin chips without damage. Generally, with the chips getting thinner, chipping can gain influence. Thus a vision system is recommended. A crack of some microns can destabilize a chip of some tens of microns more than a chip of some hundreds of microns thickness. The dimensions of the shell cracks can be insignificant for a thick chip.

With chips getting thinner, breaking strength is not the only important parameter to examine. As mentioned previously, flexibility is gaining more and more importance. We will show the bow/radius chips are able to reach before they break. For field applications like credit cards, this parameter is more important than breaking strength. It is important to know what curvature the chip inside is able to stand.

7. The ball-ring method can be used to measure chip flexibility. Here, r is the radius a chip can stand before it breaks, calculated by tracking s during the breaking test.

Our system for measuring breaking strength also tracks the bending of the chip. In the ball-ring method, as shown in Figure 7 , r is the radius a chip can stand before it breaks. We track s during the breaking test. Based on what s is when the chip breaks, we calculate r. The radius a chip can stand before it breaks is proportional to the square of the chip thickness.

For different etch removal amounts during the backside spin etch, we found the results shown in Figure 8 for a chip thickness of 185 µm. The chips gain strength by increasing the etch removal amount from 3 to 25 µm, but they do not gain much flexibility. Flexibility increases from coarse ground to fine ground, and reaches saturation with a 3 µm spin etch. We repeated the experiment for a chip thickness of 120 µm. In this case, we saw the same effect: With etching 25 µm at the backside, we gain strength, but see no increase in flexibility.

8. With a starting chip thickness of 185 µm, flexibility increases from coarse to find grinding, but reaches saturation with a 3 µm spin etch.

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Author Information

Werner Kröninger is a senior staff engineer, pre-assembly, at Infineon Technologies . He is responsible for the company's new developments in wafer finishing for logic devices. Since joining Infineon in 1995, he has also helped to develop the company's front-end applications such as CVD, epitaxy and tungsten. He has a master's degree in physics from the University of Regensburg.

Ludwig Schneider is a product engineer at Infineon Technologies. He is responsible for the company's wafer-thinning and CMP lines. Since joining Infineon in 1994, he has played a key role in pre-assembly production, introducing integrated manufacturing and vision inspection. He has a degree from the University of Applied Sciences, Regensburg.

Gerald Wagner is director of process development for at SEZ. His role includes wet process development for ultrathin wafers, etching of new materials and cleaning technologies. Previous activities have involved process development for polyurethane masks. He has a degree in chemistry, and a Ph.D. in thermostable resins from the Technical University of Vienna. E-mail: g.wagner@at.sez.com

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References

H.F. Hadamovsky, et al., "Werkstoffe der Halbleitertechnik," Dt. Verlag f. Grundstoffindustrie, 2 Aufl., 1990. Thin Semiconductor Devices Manufacturing and Applications Workshop 2001, Fraunhofer Institute (IZM), Munich Division. A. Böge, "Mechanik und FestigkeitslehreVieweg Verlag," Braunschweig, 21 Aufl. 1990. D. Trenkler, Master Thesis, BTU Cottbus, 2001. E. Gaulhofer and H. Oyrer, Proc. IEMT Europe 2000 Symposium (IEET/CPMT), Munich, April 2000. M. Reiche and G. Wagner, "Thinning Techniques for Ultra-Thin Wafers," Advanced Packaging, March 2003. J. Muller, P. Stampka, W. Kröninger, E. Gaulhofer and H. Oyrer, "Smart Card Assembly Requires Advanced Pre-Assembly Methods ," Semiconductor International, July 2000, p. 191.