Defect Detection Technology Transitions, Keeps Up

		At a Glance
	The vertiginous plunge into smaller geometries, coupled with the move to copper, low-k materials and 300 mm, spurs defect detection to change, adapt, and integrate. The question is whether the industry will open its wallet.

The Queen ran so fast that it was all Alice could do to keep up, but the trees and other things never changed their places at all: however fast they went, they never seemed to pass anything. “In our country,” said Alice, “you’d generally get to somewhere else if you ran very fast for a long time.” The Queen shook her head.

“Here it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run twice as fast as that.”

Lewis Carroll might have been thinking about our Semiconductor Wonderland when he penned those lines. He precisely described the endemic state of semiconductor technology, particularly as it refers to defect detection (Fig. 1).

“We’ll see some major hurdles over the next couple of years,” predicted Tom Long, corporate marketing vice president for KLA-Tencor (San Jose, Calif.). “Automated defect detection faces formidable challenges, with the simultaneous crossing of the 0.13 µm node, 300 mm and tough sub-wavelength lithography issues.”

“Some slower technologies like brightfield systems are losing steam,” said Ofer Milstein, marketing director of Applied Materials’ Process Diagnostic and Control Group (Santa Clara, Calif.). “With smaller geometries, bigger wafers and larger die processing, higher sensitivity to defect densities is needed. More on-line inspection capabilities are required, and high-throughput technologies such as darkfield inspection will find more applications.”

UV confocal tools will play an important defect detection role, according to Doug Hendricks, director of technology for TSK America (San Jose, Calif.). “The shorter wavelength gives better resolution to detect smaller defects. Confocal imaging is the other half, because it can find real defects without being swamped by nuisance defects.”

T.S. Ravi, marketing director, yield enhancement systems, at Schlumberger ATE’s Odyssey Group (San Jose, Calif.), sees no alternative but to resort to e-beam to meet new defect detection requirements. “The question is what can be done with it today, and how to offer throughputs that match optical tools’,” Ravi said.

1. Faced with the challenges of new processes and materials, defect inspection requires increasingly complex and sophisticated hardware and software, and faces its biggest hurdle: cost-efficient, production-worthy integration into the process fab line. (Source: Applied Materials)

Convergence or crash?

Copper processes are migrating from 0.18 to 0.13 µm. From a copper seed and electroplating perspective, this, added to difficulties with the use of the new low-k films and the need to fill 0.13 µm structures, presents hurdles made no easier by the 300 mm transition. There is much to be learned about ECP and unique defectivity mechanisms associated with these processes (Fig. 2). With everything converging simultaneously, yield ramping will not be a slam-dunk affair.

Like others, KLA is braced for process-oriented problems. As Long put it, “The specific tools themselves are one source of defectivity; another is process tool interaction with integrated processes. Finding process-related defects is more difficult than finding particles. As linewidths shrink, higher resolution is needed — shorter wavelengths in optical tools, or e-beam — to image smaller killer defects. When defect detection is done at the bottom of a trench or a via with a 5:1 aspect ratio with a <0.20 µm geometry, higher-wavelength traditional techniques can no longer detect anomalies. Particularly with copper, defects propagate, causing catastrophic problems at the end of the line. For instance, if the trench wall shape isn’t what it’s supposed to be, it’s difficult to deposit the right thickness of copper seed down, and this may result in copper voiding after the electroplating process. E-beam technology is required to find such subsurface voids.”

KLA has introduced a next-generation e-beam tool, which uses intelligent sampling for a production solution in detecting physical and electrical process defects in high-ratio structures.

 

Click for full-size image 2. New processes and materials are creating different types of defects. Because these reside in the subsurface, they are optically undetectable. (Source: Schlumberger)

Smaller CDs, monster chips

Die size is another complication. “We’ve seen chips 6 cm²,” said Long, adding that the defect density necessary to yield those devices at a commercial level is very low. “There are hundreds of millions of vias and contacts, plus seven levels of metal. Finding the one or two yield-killing defects is difficult.” Currently, this level of detection cannot be done in an integrated fashion because the tools required for detection are too expensive to integrate.

There is a dark side to defect detection: finding too many partial defects that neither damage yield nor cause reliability problems. “We’ve a major analysis software effort called PMC-NET,” said KLA’s Long, “aimed at the capability to isolate defects of interest from others.” Although from an electrical perspective partial defects are not outright killers, when they occur at wafer sort they impact yield and pose reliability problems; a circuit with a weak spot, such as thinning metal lines, may be a future issue.

The same is true of copper interconnect. A partial void deep in a trench can have similar results to those of an aluminum line thinned down on the surface. However, an aluminum line can be seen optically, while it is extremely difficult to detect voiding in copper. Optically invisible subsurface problems require electrical testing.

Metrology and sensors

CD and overlay metrology, from a lithography and film thickness perspective, is complicated — particularly with gate oxides molecules thick. “As the process window continues shrinking,” said Long, “the technology required to identify excursions becomes more technically difficult. If the uniformity of a 300 mm deposition process decreases, followed by decreases in CMP, litho and etch process uniformity, metrology control problems can easily become systematic defectivity problems. Systematic defect problems, such as under-etched contacts, vias or damascene trenches, require sophisticated e-beam or UV optical inspection technology.”

Integrated metrology for defect inspection is desirable, but faces problems as the 0.13 µm border is crossed. The state-of-the-art necessary to capture relevant metrology and defect signatures is available only in a stand-alone environment. Equipping each tool with sensors to detect a particular defect or metrology problem may not be what is needed. The manufacturer could spend a lot and still require more sensitive stand-alone measurement. So although work proceeds with integrated sensors, there is intense activity in the automation area aimed at layout and overall logistics in the 300 mm fab, to make stand-alone inspections more cost-effective and efficient. Eventually there probably will be a combination of integrated and stand-alone inspection.

Optics hangs on

Fabs are active in the processes of tool qualification and monitoring. Conventionally, this is done by running large numbers of monitor wafers to verify proper operation. “Once you’ve identified the need,” said Applied’s Milstein, “to improve that part of the tool’s operation information based on product wafers is required. That way, you minimize monitor wafer costs, increase tool efficiency and get a fast alert if there is an excursion. The need is for a low-cost tool with high throughput and the capability to inspect both blanket and patterned wafers.”New optics and image-processing capabilities have been added to darkfield technology, pushing up sensitivity and throughput performance. Applied has a system expected to work well at the 0.10 µm technology node and detect <0.1 nm defects (Fig. 3).

3. Designed for <0.10 µm monitoring applications, Applied’s Compass patterned wafer inspection system uses multi-perspective laser technology, with variable pixel size and angle selection, to detect defects such as bridging or missing contact. (Source: Applied Materials)

The capability of detecting particles on patterned and blanket wafers would reduce the need for monitor wafers, making better statistical data available because the platform’s throughput would permit inspection of every wafer. This would lead to tighter process control and fewer excursions. Eventually these tools would be integrated into the platform and track wafers as they travel from one chamber to the next, and as they go through inspection at the end of the process. The information would be fed automatically to control and data systems, augmenting overall efficiency and process tool control.

TSK’s Hendricks believes UV confocal tools will play a central role in defect detection. “If you inspect metal lines and have CMP oxide underneath, there’s a color variation. Run at high sensitivity, a regular inspection tool sees this background color variation as a difference, falsely flagging it as a defect. Confocal imaging provides a narrow z slice, and you only see the metal layer — not the underlying oxide — so color variation isn’t a problem.” (Fig. 4)

Confocal offers other advantages, as in the inspection of grainy materials such as polysilicon or aluminum. With a regular inspection system, the grain shows up as defects. With a confocal system it is possible to set the focus point at the bottom of the space, where the defects of interest are. If there is a thin stringer down in the bottom of the space, the confocal z slice can be set to view it without seeing the tops of the lines from where nuisance defects originate.

4. Confocal microscopy provides a shallow depth of focus and z height optical sectioning, which enables the inspection to concentrate on real, rather than nuisance, defects. (Source: TSK)

Hendricks does not believe larger dice and wafers will affect inspection. “Smaller design rules will have a major impact,” he cautioned. “Inspection platform suppliers must migrate to shorter wavelengths, just like stepper suppliers have, with wavelengths moving to UV and then to DUV.” Optical inspection will not meet fundamental limits anytime soon. However, it is understood that at the 0.10 µm node, with <0.10 µm sensitivity requirements, even DUV may not cope. “At some point it’ll be necessary to switch to something new, be it SEM or some of the novel optical approaches being investigated.”

Rajiv Roy, vice president of STI (Plano, Texas), believes all microscopes will be automated, both for stand-alone inspection and in situ. “There is a trend away from high- to low-end equipment, because in a 0.13 µm process not all defects are at that node. There are many boulders,” said Roy “and manufacturers want lower-cost equipment with an 80 wph speed to quickly screen out the big issues. This isn’t only for standard post-etch. It’s happening for post-develop and every process point where wafers are looked at through microscopes.”

There are other areas, such as reticle inspection. “There are high-end tools for reticle inspection,” said Roy, “but you don’t want to do a high-end inspection whenever you pull a reticle to use it. Some operators use lights to do a cursory check and determine if there are any gross particles that they can detect — this must be automated.”

Defect-free reticles are difficult to make, and pattern transfer at 0.13 µm poses problems. This begins at the design and design correction stages, leading to optical extension technologies, phase shifting, and OPC performed on high-density, tight-spaced designs to obtain a printed image as close as possible to what the designer wants. The move to shorter wavelengths has tightened process latitude because the effort to enhance resolution results in a smaller process window. Moving from the reticle to the printing and then to etching is becoming increasingly difficult. Add to this that under certain conditions, at shorter wavelengths, degradation occurs within the reticle’s pellicleized portion, changing its characteristics.

As circuit performance and clock rates soar, many defects show up as hard-to-detect CD errors. Requirements for 0.13 µm lithography are so stringent that subtle CD errors, capable of affecting a circuit’s clock rate by creating a delay in a line that is narrower than it should be, are creating much concern.

These reticle CD errors are on the order of 40 nm or less. When they print, this is reduced to about 8 nm. If lines narrow in an area where a trench is defined in a copper process, seed deposition problems may occur. If there is a thin area within the electroplating process, a difficult-to-detect void can result. This kind of variation across a circuit with 3 miles of interconnect lines per level is nightmarish to find and is one of defect detection’s biggest issues.

Process diagnostic platform manufacturers are working on image-processing rates 16 times higher than what they were a year ago. With the move to smaller pixels, formidable image processing capabilities are needed to process data at a fast rate, get economical inspection times with large wafers and find these small defects.

With bump inspection, defects 5.0 µm and larger are sought, and metrology is required. “You’re measuring things on the wafer — bumps, their width, diameter and height, as well as the size and position of probe marks,” said Tom Verburgt, CTO at August Technology (Edina, Minn.) “Probe mark inspection is another trend. As fabs do pad shrinks, they must monitor probers and probe mark locations on the devices, and track whether the probers are drifting out of spec before damage occurs.” Some CD measurement is required to evaluate the positions of the vias before putting the bumps on the device.

“We are seeing non-standard inspections in various environments,” said Verburgt. “Approximately 50% of our systems are customized for a unique process, such as micromachine and GaAs devices. There are people making devices that aren’t even square, which presents interesting requirements, particularly since inspection systems tend to assume that dice on wafers have an array pattern. With micromachining, devices aren’t even flat and have different geometries in the z direction, requiring 3-D inspection.”

The e-beam age

Much of the defect detection effort is shifting toward electrical defectivity, which allows in-process electric killer defect identification. E-beam platforms can determine if there is a physical signature that signals that an electrical problem may occur. If there are 500 defects on a wafer, and only three can kill the circuit, electrical defectivity identification will show where they are.

Applied agrees that e-beam inspection will become mandatory. “There’s already a demand for e-beam tools,” said Milstein, “but not necessarily to detect smaller defects. Optically, we can detect non-resolved defects with a darkfield system because it’s designed to detect the presence of a defect and not necessarily provide data on its type and kind.” However, Milstein added, eventually an off-line or stand-alone SEM review tool will be needed. “We’ll see more SEM inspection tools — not necessarily for smaller defects because low throughput is still an issue — but for high-aspect-ratio specific applications such as voltage contrast defects, which darkfield systems can’t detect.”

Over the next two or three years, e-beam tools still will be unable to provide fab-level throughput. A high-throughput system solution is needed; however, it would require a smart system to reroute the wafer for in-depth analysis of the defect detected. “An interim solution might be to use SEM review systems with specific capabilities and application to detect these process defects, based on intelligent sampling,” explained Milstein. “More automation and data gathering and mining is needed. Defects must be analyzed as to structure, material, composition, etc., to target sources. This requires complementary tools to prop today’s technology’s weaknesses.”

To tie everything together and execute timely corrective actions, software capable of collecting and analyzing these data to provide solutions is needed. This goes beyond systems that merely identify defects and their types, to those that provide direction on defect sources and corrective actions. This requires software connectivity to the various fab systems and knowledge. The software would not only coordinate these data, but also provide information on the defect, based on additional sensors or characteristics. This will require higher sensitivity levels, while maintaining, or improving, throughput.

Fabs are interested in e-beam tools as an in-line mode wherever sampling takes place. “There are regions inspected at high resolution, not the entire wafer, but just certain areas for each die,” said Schlumberger’s Ravi, adding that one-hour, full-wafer inspections eventually will be possible. In the meantime, e-beam inspection has been very effective in isolating process-related subsurface defects such as high-resistant contacts and post-electroplating copper dual-damascene voids. This is important because void excursions are always possible.” (Fig. 5)

5. Optimizing beam current and energy control for voltage contrast and surface charging enables e-beam tools to identify (right) voltage contrast defects that previously might have gone undetected (left). (Source: Schlumberger)

Low-k is another hurdle. “There aren’t too many issues now,” said Ravi, “but <3.0 low-k materials pose process-related problems with dielectric-constant variations within the die or even adjacent copper trenches. E-beam can also spot these.” In terms of defects, the biggest low-k issues are how well controlled the dielectric constant is and the defect types that come up, such as post-CMP copper stringers. In carbon-doped low-k oxides, for instance, carbon erosion can occur during etching that adversely affect dielectric constant and device speed.

“We’re aiming for early small-defect detection — <0.10 µm,” said Ravi. “Many 0.18 µm-technology killer defects are 0.10 µm or under. How fast you scan with e-beam isn’t critical; how fast you inspect is. You can scan quickly and locate big defects, but you’re really not finding the small, optically undetectable killer defects.”

The question remains whether e-beam tool throughput and MTBF can be increased to the point where it can replace optical. Careful trade-offs will have to be made. Although e-beam does not match optical in terms of speed, with smart sampling it is adequate for in-line applications; throughput capabilities of e-beam inspection are 15 to 200 cm² per hour, depending on the inspection sensitivities required. In general, MTBF is improving. It is expected to reach optical inspection levels within a year or so.

Electrical testing is a sound alternative to writing off advanced metal layers as uninspectable due to the metal grain problem, which swamps existing inspection tools with nuisance defects. However, electrical testing is a painful procedure because it cannot be done until the wafers reach the end of the line. This can mean a week or more delay; meanwhile, the line can fill up with bad wafers.

With electrical testing a manufacturer may go through the loop three or four times before finding a defect. Then he optimizes the process and tweaks the etcher, CVD or whatever tool is deemed appropriate. Afterwards, it is necessary to determine if they were tweaked in the right direction. This means running wafers and another electric test and a long wait for results, often to find the knobs were not tweaked far enough. So the process is repeated.

This can be done statistically, rather than serially, executing several runs simultaneously with different tweaks. This is Intel’s way. The company runs fractional factorial statistical design experiments, optimizing the process after the first or second loop. Often this works well, requiring only two or three weeks to get feedback. Sometimes, however, it still can take several loops before the process is corrected, as well as many expensive wafers; and, in the end, only one defect problem has been solved.

Just finding defects is no longer sufficient. A total solution is needed that detects, identifies, corrects and closes the loop. Defect detection can no longer be done piecemeal, in a vacuum. The industry must understand — and, to a large extent, does — that inspection problems grow exponentially worse as design rules shrink. However, we tend to be complaisant and say, “Yes, the problem will get a little bit worse, but we’ll get by — we always have.”

The reality is that the inspection problem is not going to get a little bit worse — it is going to get a lot worse! Experience tells management it takes x% of the budget for defect inspection, and they may think that essentially the same model and percentage can be retained. It is not going to work; defect inspection costs are going to rocket up faster than those for other tools because the job is that much more difficult, and this is not going to change any time soon.

Brace yourself for sticker shock. •

The Next Step: Three-Dimensional Characterization Janet Teshima, Product Manager, IC Failure Analysis, FEI Co., Hillsboro, Ore.

New materials and semiconductor processes — copper dual-damascene, low-k dielectrics, and CMP for both copper and shallow trench isolation — generate new levels of yield-limiting defects below the wafer surface, among multiple layers. Defects that used to show up on surfaces in the aluminum processes are now at the bottom of vias in copper processes. These add challenges to the defect review, characterization and sourcing processes. FEI’s Structural Process Management approach allows 3-D visualization and chemical characterization of subsurface structures. Cross-section of a copper device. (Source: FEI) Hundreds of wafers are inspected by optical- and laser-based tools every hour in a fab to quickly detect and map defects; collect statistical data on defect density, distribution and size; and define location coordinates. Wafers requiring further characterization are transferred to an optical microscope to capture images and view subsurface details. Using inspection-tool coordinate information and optical image sampling, specific defect sites are located by a SEM review tool. SEM provides 2-D imaging, verification of proximity to the surface or sublayer and chemical identification. However, sometimes the defect must be characterized in 3-D to reveal structures beneath the surface, to determine the defect’s root cause (Figure). The 3-D subsurface defect characterization process has been made less operator-intensive by software that accepts data files from optical or electrical inspection tools, identifies and locates the sample area to be prepared, and controls ion beam position and etch parameters. High-resolution chemical analysis is possible with energy-dispersive X-ray spectroscopy (EDS) and automatic grain size analysis. The technique also impacts ramp-up to high-volume production when wafers are identified with systematic defect types. FIB/SEM systems can investigate the wafer and the information used to eliminate the cause. Incorporating these analytical tools into the fab reduces the overall yield learning cycle by providing quicker, more detailed, 2- and 3-D defect information, as well as elemental analysis for defect identification. •