Selective Epitaxy Falls into Favor

Selective epitaxy has never been the most popular process on the block. In fact, "few selective deposition processes have done much but boost their blanket deposition counterparts, as was certainly the case with tungsten," said Chantal Arena, director of epitaxy technology development at ASM America (Phoenix). "But epi's situation is changing now with the growing demand of source and drain (S/D) elevation, especially critical for SOI technologies and the advent of recessed S/D to locally induce a so-called uniaxial strain in the transistor channel."

Strained silicon channels allow higher electron and hole mobilities, and are compatible with mainstream CMOS processing. In strained silicon, the silicon lattice is stretched (tensile strain) or squeezed together (compressive), causing the charge carriers in silicon (electrons and holes) to move faster in response to applied voltage. Miraculously, strained silicon is allowing device manufacturers to improve performance without traditional scaling. "For a given technology node, you can always trade off power and speed. However, with strained silicon, we can shift the I_on/I_off curve, increasing drive current or lowering leakage without sacrificing the other, said Arkadii Samoilov, senior technology manager of the epitaxy product unit at Applied Materials (Santa Clara, Calif.). "Our partners and customers report over 35% improvement in saturation drive current for PMOS devices using SiGe epi. No other transistor manufacturing step has provided that kind of improvement."

Although the use of a S/D "stressor" is an effective method for introducing uniaxial strain in a transistor channel, most other films and structures introduce some stress, notably the shallow trench isolation, silicides, metal gate and purposely stressed liner films. With scaling, it is important to model the effects that various processes and materials have on carrier mobility in the CMOS channel.

Selective epitaxy is a very small market relative to blanket epitaxy, but it is rapidly growing. The silicon and SOI wafer manufacturers serve the broader epitaxy market.

1. The Epsilon epitaxial reactor has a parallel gas flow process chamber for low gas residence time, ensuring uniformity and repeatability of very abrupt structures. (Source: ASM)

Selective epi got its start in manufacturing heterogeneous bipolar transistors (HBTs). Hitachi, Infineon, Agere and others have reported use of selective SiGeB and SiGeB:C epi for depositing the base of the HBT. It was followed by elevated S/Ds for CMOS devices, according to Samoilov. SOI technologies have serious silicon real estate limitations, which require additional epitaxial silicon on the S/D to facilitate contact silicidation. "Selective epi applied in recessed S/D to stress the transistor channel is a recent application, first described by Intel. Today, recessed and elevated S/D can be processed in one epi step, even when different materials are used," explained Arena. Figure 1 shows a 200 mm epi reactor chamber.

For its 90 nm process, Intel has stated that it is using strained silicon in volume manufacturing. Figure 2 shows the PMOS and NMOS uniaxial strain approaches and TEMs of the transistors. Selective epi of SiGe with boron doping is performed for the PMOS device, using 17% germanium content.¹ Germanium in the silicon lattice causes a compressive stress in the channel between the recessed S/D, thereby increasing transistor drive current. Intel reported a 25% increase in saturation current (I_dsat) and a 50% increase in linear current (I_dlin). The report emphasized that a larger ratio between the depth and width dimensions of the channel resulted in larger stress. The boron allows a higher active dopant concentration in the S/D than with implantation, further increasing drive current.

2. SiGe in PMOS devices provides a faster pathway for holes to flow across the channel, from source to drain, whereas in NMOS devices, electrons are the charge carriers, requiring a tensile strain across the channel. (Source: Intel)

Later, Texas Instruments reported 35% and 70% increases in I_dsat and I_dlin, respectively, using a prespacer approach and thus placing SiGe areas closer to each other in devices.²

3. Strain simulation in a PMOS device with recessed SiGe S/D. Colors represent different levels of strain in the channel; measured at 1.2 GPa in the middle of the channel. (Source: Applied Materials)

The etch step and clean that precede the embedded S/D epi are crucial (Fig. 3 ), since the etch profile and area significantly effects device performance. "Work on the wet clean and epi process is needed to make sure that not only all the residues are removed, but also that the shape of the S/D recess does not change after etch, said Samoilov. "Ultralow-temperature pre-epi bakes are required to eliminate any silicon mass transport in the recessed areas."

Intel's U.S. Patent³ stated that a similar approach could be used for the NMOS transistor, using silicon doped with carbon instead of germanium, and opposite in situ doping with arsenic or phosphorus instead of boron. Chris Werkhoven, vice president, strategic marketing at ASM America, noted, "One advantage to the Si:C approach is that HBT device makers already use carbon-doped silicon epi processes, and we can transfer that knowledge immediately to our CMOS customers."

LETI has investigated using Si:C in NMOS channels, but Samoilov said, "Further process improvement of the Si:C process to increase the tensile strain is one of our most immediate challenges." Meanwhile, the tensile nitride serves to spread the silicon lattice in the NMOS channel and speed performance by ~10%. Other device manufacturers are using strategies such as ultrathin multilayer nitride stack to gain increased speed in the NMOS channel. However, the nitride approach is not as scalable as carbon-doped silicon.

Samoilov noted that for those designers who want to have a comparable performance of NMOS and PMOS, the strain-induced improvements of PMOS are great news. "The drive current increase in PMOS due to SiGe puts significant pressure on finding an equally powerful solution to improve the NMOS drive current," he said.

4. The low threshold voltage target for a PMOS device is met using a strategy including boron delta-doped strained SiGe channels. (Source: TSMC)

High-performance logic is not the only major driver of strained silicon technology. Low-standby-power applications, which may be the first adopters of high-k gate dielectrics, may use high-k/poly gate stacks if the problems of Fermi-level pinning and the associated high-threshold voltage problems can be solved. Howard C.H. Wang and colleagues at TSMC (Hsinchu, Taiwan) will present results on low-power devices next month,⁴ demonstrating how low threshold voltage (V_t) control has been obtained using a boron delta-doped strained SiGe channel and high-k dielectric (Fig. 4 ). TSMC uses a selective epitaxy-grown strained silicon channel to achieve ~200 mV PMOS V_t reduction, while the same process with an in situ boron-doped sacrificial silicon cap further reduced V_t by another 300 mV. The delta-shaped boron profile helps avoid short channel effects. Thus, selective epi helped lower V_t to the critical target of 0.3 V, which will be required for certain low-power circuits.

Locally applied uniaxial strain is considered more efficient at boosting PMOS transistor performance than biaxial strain. Biaxial strain, or global strain, is typically introduced by growing a thin silicon layer on a thick, strain-relaxed layer of SiGe so that the former develops a tensile stress. This is mostly done on a wafer or global level with blanket epi layers. Biaxial tensile strain significantly enhances the performance of NMOS transistors, but not PMOS transistors, unless the SiGe layer has a germanium content of 35% or more. Using SiGe, threading dislocations can form and cause yield problems, unless the epi process is fully optimized. "Recent work by Freescale showed no degradation of device properties," said Chris Werkhoven, vice president of Strategic Marketing at ASM International.

Interestingly, manufacturers of epi reactors compete with wafer suppliers, but also partner with them. Soitec (Grenoble, France), as the leading suppler of SOI wafers, has begun producing sSOI. Last month, the company introduced uniaxial germanium-free strained silicon wafers with 40 nm silicon thickness using ASM's epi processes. Earlier this year, Soitec and Applied Materials announced a collaborative program to develop germanium-on-insulator substrates for 45 nm and beyond. Applied Materials and Silicon Genesis (SiGen, San Jose) have developed an in situ SOI smoothing process using epi reactors. SiGen also produces an sSOI product.

For high-performance logic devices, most likely sSOI along with high-k dielectrics and metal gates will be needed eventually to advance the roadmap (see "The Manufacturing Outlook for High-k/Metal Gates ").

Selective epi will be important in FDSOI devices, where the silicon area is shallow (~50 Å) and in finFET fabrication, for widening the fins. Werkhoven expects certain architectures to use five or six different epi processes, and when sSOI wafers are used, one or two additional epi processes are already built in.

Epitaxy reactors

5. A single-piece, small-volume, rectangular cross-section epi chamber design provides leak tightness, minimum turbulence and wafer uniformity control. (Source: ASM International)

Werkhoven stated that properties such as low gas residence time, and minimum turbulence with a parallel flow design of the chamber all contribute to better controllability and reproducibility of the process (Fig. 5 ).

Like many other front-end processes, epitaxy has progressed from a relatively high-temperature process (~900°C) to a lower-temperature process (700-750°C), because of dopant diffusion concerns. The only selective epitaxy processes for which dopant diffusion is not a concern is the buried channel, which is put in place before any ion implantation steps. After isolation, the active region is coated with a thin SiGe channel, followed by silicon epitaxy.

Integration challenges drive epi process temperatures down further, but "every time you decrease the deposition temperature by 50°C, the process requirements challenge the performance of your hardware," said Arena. She added, "The reactor fluid dynamic characteristics are very important, and the chamber has to be extremely leak tight to keep moisture and oxygen levels at their lowest values." For a 600°C deposition, part-per-billion levels of oxygen and moisture are required, and for that, the length of O-ring used to seal the reactor has to be minimized. Samoilov said that maintaining a clean chamber and having the ongoing ability to process wafers at lower temperatures will be critical to expanding SiGe processing to pure germanium epi on silicon, which occurs at ~400°C. "Germanium on insulator is very compatible with high-k and metal gate processing, and we may see these processes as early as the 32 nm node.

"The biggest yield hits come from loss of selectivity. Having a small chamber volume helps to maintain an extremely clean environment in the reactor, which is crucial to avoid nucleation on dielectric layers. Furthermore, small reactor length allows more efficient utilization of gases to increase the selectivity process window," said Samoilov.