Elevated Source Drains: Still a Contender
Peter Singer, Editor-in-Chief -- Semiconductor International, 8/1/2000
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It's still necessary, however, to form a contact to these very shallow junctions. A potential problem is that contacts are traditionally made with silicides, typically TiSi2 or WSi2. A thin layer of the metal (Ti or W) is deposited on top of the silicon by sputtering, and the silicide is formed by reacting the metal and the underlying silicon with a rapid thermal processing (RTP) step. Through this process, a small amount of the silicon - the silicon of the source/drain - is consumed. Though small, this consumption of silicon is increasingly a larger percentage of the overall thickness of the source or drain. Although the silicide thickness has been scaled down (to avoid increased leakage from the proximity of the silicide/silicon interface to the junction depletion region), the amount of scaling is limited.
The bottom line is that the combination of a shallow junction and a thin silicide contact can lead to unacceptably high resistance in the device. According to the International Technology Roadmap for Semiconductors (ITRS), the parasitic device resistance should be no more than 10% of the channel resistance for the 100 nm technology node and beyond. It's questionable if traditional techniques can meet that goal.
Elevated source/drains provide a way to avoid the parasitic resistance increase while still maintaining shallow junctions. Elevated source/drains are fabricated by raising the level of the source and drain by selective silicon deposition. The extra silicon increases the process margin for the silicide process and extends the latitude for contact junction design. To maintain a similar crystalline structure, the extra silicon is "grown" by silicon epitaxy.
Selective epitaxial growth (SEG) - actually selective growth or deposition of any kind - has always been somewhat tricky, the trick being to make sure the material goes where you want it, with none being deposited elsewhere. However, SEG could be one step closer to production thanks to new research at Motorola's Advanced Products Research and Development Lab (APRDL, Austin, Texas). Researchers there have developed a robust, low-thermal-budget, high-quality SEG process using a commercial RTCVD reactor. The work, reported in the Journal of Vacuum Science and Technology B (Vol. 18, 2000) shows that by controlling duration of the HF clean step in the preclean sequence prior to SEG results in a desirable undercutting action that leads to facet-free epitaxy. They claim undercutting the liner oxide and silicon growth under the nitride spacer recesses the silicon-linear oxide interaction away from the source/drain region. This gives extra thickness in the source/drain region before the increase in silicon-nitride interface energy causes the SEG to facet.
With developments such as this, the elevated source/ drain structure remains a contender, providing "a promising route to achieve shallow contacting junctions, reduce overlap capacitance and simultaneously reduce parasitic resistance increases," according to the Motorola researchers.
Moto's GaAs Fab Converts to 6-inch
Motorola Inc. (Phoenix, Ariz) completed the process of tripling the wafer output of its Compound Semiconductor-1 (CS-1) wafer fabrication facility in June - a full three months ahead of schedule. All of Motorola's GaAs semiconductor devices are currently fabricated in the CS-1 facility. By converting the CS-1 fab from 100 mm to 150 mm wafers and equipping the facility to maximum capacity, Motorola has increased the total die output of the facility by a factor of greater than three. The CS-1 manufacturing facility is one of the industry's first GaAs fabs in production to be fully converted to 150 mm wafers for all GaAs technologies - including implanted MESFETs, pHEMTs, and HBTs. With this capacity increase, the Motorola CS-1 fab is now the largest rf GaAs facility in the world.
Motorola officially received initial QS-9000 certification of its CS-1 facility on July 1, 1999, and passed re-certification for the second time on May 25, 2000. The third-party certification to QS-9000 also results in registration to ISO 9001.
