Mood Swings at SEMICON West
SI Editors -- Semiconductor International, 7/1/2000
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At a Glance | | |
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Advanced lithography
New approaches continue to make inroads among different lithography technologies. So while ion projection lithography holds Europe's interest and X-ray is still fashionable in Japan, some of the relatively newer techniques — such as extreme UV (EUV) and 157 nm — appear to be making greater strides compared with a few older methods such as X-ray or even SCALPEL. Among the next-generation lithography (NGL) techniques, Nikon, in collaboration with IBM, introduced Projection Reduction Exposure with Variable Axis Immersion Lenses (PREVAIL), an electron projection system. To get around throughput-limiting small projected sub-fields and Coulomb effects typical among charged particle systems, PREVAIL dynamically corrects for off-axis aberrations and reduces Coulomb interaction effects with a high-emittance electron gun. Nikon expects throughput of 30, 200 mm wafers per hour.
 DTF-8 deep-UV resist can achieve 0.2 µm CDs in 3.0 µm of resist using binary masks. It can provide 15:1 aspect ratio isolated structures. (Source: Clariant Corp., AZ Electronic Materials) |
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Wafer processing
In wafer processing — technologies such as ion implant, deposition, etch, CMP and thermal processing — expect to see a strong focus on four key areas:
- Introduction of new materials into the manufacturing process, especially copper, low-k dielectrics and high-k dielectrics.
- Continued scaling leading to thinner films and smaller geometries.
- An increased emphasis on single-wafer and small-lot processing.
- The move to 300 mm.
The shift to new materials is driven largely by the desire to increase chip speed and reduce the number of metal levels. A move from aluminum to copper as the main interconnect material reduces resistance, for example, and the move from silicon dioxide to materials with low dielectric constant (low-k dielectrics) reduces capacitance. These material changes reduce "crosstalk" and signal time delays. There also is interest in materials with high dielectric constants (high-k dielectrics) to replace more traditional dielectrics for memory cell applications, where it's desirable to have a higher capacitance to store more charge in a smaller space; and as the gate dielectric, where it is desirable to have a thicker dielectric yet still maintain the ability to turn the transistor on and off.
The move to copper and low-k dielectrics has presented many challenges, and only a handful of chip companies are expected to have copper into production by the end of this year. A new deposition technology — electrochemical deposition (ECD) — had to be developed for copper, and suppliers are still working to fine-tune the process and the chemical cocktail that is the electroplating bath.
 The UI-5000 SIMOX ion implanter features high implantation uniformity, high current of 100 mA and 300 mm capability. (Source: Hitachi America Ltd.) |
Low-k dielectrics can be deposited by CVD or spun on, depending on the material. Although IBM (East Fishkill, N.Y.) made news recently with its announcement to standardize on Dow Chemical's (Midland, Mich.) SiLK spin-on low-k product, other choices remain viable — and are sure to be a hot topic at SEMICON West. Another challenge, beyond obvious things such as adhesion and other mechanical and electrical interface issues, is the fact that copper must be patterned with a "dual-damascene" approach, wherein holes and canals are etched in the dielectric layer and the copper then deposited into those holes and canals. This is followed by a copper CMP step. Dual-damascene represents a dramatic departure from traditional process flows.
Although most people now assume the semiconductor industry will continue to easily overcome any challenges associated with the move to ever smaller geometries — 0.18 µm is now in production and 0.15 µm in development — the trend still creates a wide variety of problems in wafer processing. Most notably, the higher aspect ratios (AR) of features make it increasingly difficult to get materials — be they water, etching gases or photoresist — in and then out of deep holes. High AR features also create problems with filling and step coverage.
The move from 200 mm to 300 mm wafer sizes, although long in the making, is finally happening. This brings great joy in Equipmentville, where, after spending millions (collectively probably billions) to develop 300 mm capabilities — including "bridge" tools capable of both 200 mm and 300 mm processing — suppliers might finally get to see some return on their investment. At SEMICON West 2000, expect to see a renewed emphasis on 300 mm capabilities.
Also expect to hear more discussion of single-wafer and small-lot processing. This has slowly been happening, led by a desire to increase fab flexibility and have more control during each process step; but the move to 300 mm could enable a sudden shift to single-wafer since almost everything needs to be resized anyway.
Metrology
SEMICON West exhibits will demonstrate that metrology continues as a key enabler for the development and manufacture of increasingly complex semiconductor devices. Providers are discovering that fabs require faster, shorter development time of metrology capabilities to cope with new processes, particularly in the case of photolithography, copper and CMP. These needs are accelerating the migration of metrology from off-line to in-line and in situ. The move toward integration is speeding up, and several of the minor suppliers are finding it difficult, even during the current upturn, to allocate needed R&D funds to enable their products to meet semiconductor manufacturers' demands.
It appears existing technologies for sensor-based process control, in-line microscopy, focused measurements for interconnect fabrication and development needs will continue to serve manufacturers well until the industry moves beyond the 0.10 µm node. However, some areas will have to evolve faster, due to the introduction of copper interconnects, low-k films and dual-damascene process flows.
The move to 300 mm wafers is forcing in-line metrology suppliers to focus increasingly on non-destructive testing of product wafers. This requires sensors to progress from essentially indirect measurements of wafer level properties to far more detailed information obtained though vastly improved optical resolution. One of in situ metrology's principal challenges is, and will continue to be for the near future, how to make a direct measurement without introducing factors that might alter the focus of the measurement, such as within an etch chamber.
Automation continues making inroads, as tools considered engineering-intensive, such as FIBs, SEMs and others, are becoming more software-driven. The move also is being stimulated by increasing demand for automated defect detection. Near-future measurement requirements are causing the merger of metrology techniques traditionally considered as stand-alone units into fully integrated multi-capability systems. This is leading into an era of modularity, in which the semiconductor manufacturer is able to select platforms of modularized capabilities, which enable him/her to configure the system in accordance with the necessities of the product and the technology node in which he/she is working, cutting costs.
Yield management
Production-level yield management for 0.18 µm technology devices targets delivery of capable real-time monitoring and control strategies. The differentiation between yield-impacting and non-yield-impacting defects is increasingly critical to high-throughput production. The feedback loop for defect review and characterization also must be condensed to ensure defects can be traced to their source before a significant number of wafers are affected.
More than ever, yield ramping depends on the identification of critical process parameters as they affect yield. Greater monitoring and control resources must be dedicated to the new, relatively immature process technologies of CMP and electrochemical deposition. Also, failure mechanisms can be different when new materials are involved. Copper CMP, for instance, is a crucial process step that requires a high level of characterization and monitoring.
Companies also must rapidly incorporate and optimize new processes. For example, wafer backside decontamination with a chemical etch processor from SEZ (Phoenix, Ariz.) must be optimized to completely prevent copper contamination and minimize hot spots that affect the lithography process.
Though metrology and yield management purchases are becoming easier to justify, especially at 300 mm, the procedures must be in place to most effectively utilize the new tools. As has always been the case, incompatibility between different databases of information will continue to inhibit the yield management process. With an ever-growing mound of inspection and electrical data, high-level data management is becoming essential. Relational databases are being improved.
The value of monitor data, from development to high-volume production, changes dramatically. To improve the fab's monitoring and control strategy, engineers must take a dynamic approach to utilizing yield management information in each of the stages of production (R&D, pilot, full production, mature production) so that mature and no-longer-useful monitors are systematically eliminated for high productivity, while new monitors are adopted for the next technology generation.
Finally, calibration, monitoring and simulation tools are increasingly necessary, especially in lithography cells where imaging below the wavelength of light requires assistance for manufacturability.
Assembly & packaging
Co-design of chip and package is a growing trend. For leading-edge products, the interconnect traces in these packages can function like transmission lines and therefore become a part of the load the chip sees. Microvia packages and board patches are where most of this transmission line effect takes place, and capability for making them is getting very mature.
For applications such as cellular phones and personal digital assistants, space limitations are determined more by passive components. Making smaller passive components for surface mounting is extremely challenging. System-in-a-package (SIP) schemes under development are embedding these passives in the package to make them smaller.
There is a lot of potential for improving volumetric efficiency by stacking dice in a package, thinning dice and removing unnecessary material. Three-dimensional stacking of memory dice in a package continues, and schemes for area-array connection of multiple dice are entering the proof-of-concept stage.
Though there is some debate about its need, lead-free solder is becoming a requirement in electronic systems, which will affect flip-chip attachment as well as board assembly. Consensus seems to be forming about which lead-free solders to use, but there has not been as much coordination with their higher temperature needs and the reliability of upcoming low-k dielectric materials on the chip.
More wafer-level packaging schemes are including compliance between the chip surface and the next surface. Many wafer-level packages use large solder balls to provide this compliance. Examples of the new trend are Tessera's (San Jose, Calif.) WAVE technology and Georgia Tech's compliant wafer-level package (CWLP). The CWLP method uses a dielectric material that is compliant enough to absorb shock in use, but stable enough to use as a base for plating copper leads. After those leads are plated, another coat of dielectric is applied and openings are made. Solder is then plated onto the ends of the copper leads. WAVE uses interposer containing leads, which are attached to the pads on the wafer all at once. An underfill is added between the wafer and interposer in a molding-type operation.
Some connection technologies have emerged that can serve as compliant leads or probe contacts for testing (See Assembly & Packaging). Form Factor (Livermore, Calif.) makes microsprings by first using a wirebonder to attach gold wires of a chosen length and shape onto the wafer. The wires are then plated with other metals to add stiffness. Nanonexus, a Fremont, Calif.-based spinoff from Xerox, takes advantage of a stress gradient in a metal film to make lithographically definable spring contacts that simply curl up.
Factory automation
As 300 mm manufacturing starts to take place, increased automation will be needed not only for material movement, but also in scheduling, tracking and yield management. Anything that could cause a tool to be idle, or a wafer to be scraped, yield poorly or bin out at a low performance level will be about 2.5 times as expensive compared to 200 mm manufacturing. Many of the methods for avoiding these problems require effective automation and computer-integrated manufacturing.
From the beginning, 300 mm fabs will be built for automation. The ergonomic concerns with handling a 25-wafer FOUP along with the need for continuous processing make it essentially impossible to function without a high level of automation. Standards are now in place that unify physical characteristics of carriers, loadports and vehicles, as well as the data management capabilities of tools. As a result, factory integration will be much more seamless.
Also included in the standards is the requirement for tracking multiple products in a carrier. Business needs such as cycle time reduction and lowering the risk of excess inventory falling in value will force fabs to be more flexible. It is conceivable that a fab may need to make, for example, only two wafers of a particular product while making other products as well. Making enough of that product to fill a carrier might be inadvisable, and running two wafers alone may interrupt the manufacturing flow too much to be justified economically.
Yield management for 300 mm manufacturing will require a vast data collection and analysis effort, much of which will have to be automated. The need to reduce the number of scrap wafers alone will require that excursions be corrected more quickly. Some of the data analysis that is now done when an excursion is detected must be done constantly in the background just in case it is needed.
Advanced process control methods, such as run-to-run control and feedforward, are being implemented more. Many of these schemes provide automatic recipe adjustment to keep wafer state parameters as close as possible to their nominal values. Many methods involve short loop control, meaning data will be collected and analyzed every time a lot, or even wafer, is processed. This level of control must be automated if it is to be successful.•
