Packaging Provides Viable Alternatives to SOC

		At a Glance
	While many people concentrate on the ability to integrate more functions on a single chip, advances in packaging provide alternatives that are sometimes much better. In addition to being more difficult to package, a large-die IC can yield too poorly to justify economically. As the industry starts to take the package into account with IC designs, the package can be designed as an integral part of the system rather than just a carrier for the ICs. Some see the critical path for realizing a breakthrough for system-in-a-package to be the development of design tools, not materials or technology.

As the demand for more functionality in electronic systems continues to grow, more effort goes into developing system-on-a-chip (SOC) designs and devices. It certainly is possible to integrate logic, analog and memory functions on one silicon IC, though the cost of doing so can be high. If the increased cost of this integration can be justified, an SOC is a readily available option.

For decades, the least expensive way to add more functions to an electronic system was to integrate more functions on a chip. IC manufacturing, though, is entering new territory, where delays for longer on-chip interconnects are starting to have a significant impact on the IC's performance. Putting circuit components closer together by putting them on the same die will not necessarily improve signal propagation time between them.

Also, once a die's size reaches a certain point, its yield starts to drop significantly. Going beyond that point makes little economic sense. This effect doomed the 1980s version of the SOC concept, wafer scale integration.

In some cases, ICs that logically belong together to form a system or subsystem cannot be made on a single die, such as an rf frontend module, which requires both silicon and gallium arsenide components (Fig. 1). High-density packaging technology has advanced to the point where intentionally splitting a leading-edge, single-chip system into multiple dice can provide a performance advantage as well as a cost advantage. As Figure 2 indicates, systems-in-a-package (SIP) are expected to hold a significant market share in the 2003 time frame, offering a favorable combination of cost, speed and density.

Even though some systems are better realized on a single chip, it is not likely there ever will be a single-chip electronic device, like a cellular phone or PC. By the time a single-chip system is designed and made, additional capability is expected, requiring another chip. Sam Beal of Alpine Microsystems (Campbell, Calif.) noted: "We've had system companies tell us that they don't particularly believe that the system's ever going to be on the chip, because they've got a box that's a certain size, and they'll fill it up with functionality."

Ironically, the push for more functionality that is driving SOC will prevent SOC from being a complete reality. Beal continued: "I think in most devices you look at, the chip count is slowly going down, but it's not going down as fast as the integration is going up."

1. The HiperLAN module contains gallium arsenide ICs, silicon ICs, passive devices and interconnects that were all co-designed to optimize the module. (Source: Intarsia)

System-on-a-chip

Depending on the particular application, system-on-a-chip can be the best solution. The 1999 ITRS Roadmap has a chapter devoted to SOC, and it proposes a cost analysis based on yield models.¹ From a packaging perspective, SOC can be an improvement. The assembly and packaging chapter of the Roadmap gives an example of combining a DSP and its controller in one chip, which are both pad-limited. Since the combination of the two has fewer total I/Os, this leads to a smaller silicon area, which can yield better, and a single die that is easier to package.

The plans for SOC, however, seem to conflict with current capabilities. Evan Davidson of IBM (Hopewell Junction, N.Y.) said: "If you look at the semiconductor technology Roadmap, they project out to 30 mm square chips. And I have a problem believing that that will ever be economically justifiable."

2. System-in-a-package (SIP) and multichip package (MCP) solutions are expected to provide lower-cost alternatives to system-on-a-chip (SOC) while providing the same performance. Market size projections are for 2003. (Source: Alpine Microsystems and the Gartner Group)

The yield of an SOC die is not based completely on die size. Memory, for example, can be repaired or have built-in redundancy, so it can take up more silicon area before yield drops off. Since the creation of an SOC involves the combination of many different device types, each with its own yield and economic dynamics, very detailed yield and cost models should be used in making SOC integration decisions.

Cost and performance concerns

While there can be good reasons to use an SOC design, there also are good reasons for looking at alternatives. One reason is the cost of integration.

Different technologies have a different cost per unit area, and combining them can effectively increase the cost of the less expensive technology. The approximate cost of IC functions is given in the Table.² Assuming DSP functions cost ~$30/cm², and analog functions cost ~$5/cm², combining the two on one chip can effectively increase the cost of both to ~$35/cm². If system performance improvement or value to the end customer is not enough to justify this extra cost, a multichip design would be preferred.

Table. Mixed Function Costs
•Microprocessor, DSP	$30/cm2
•FPGA	$15/cm2
•DRAM	$10/cm2
•Analog	$5/cm2
Source: Packaging Research Center, Georgia Institute of Technology

In addition to this integration cost, special structures may be added, such as deep isolation trenches to keep digital switching noise from affecting analog circuitry. This adds to the silicon area used at the increased cost level.

In addition to cost concerns, performance concerns may make a multichip system preferable.

One reason offered for the increased use of SOC is that on-chip integration allows faster interconnection between circuit components. Depending on the particular design, this may not be the case. On a large digital IC running at a high clock frequency, a signal traveling on a global interconnect trace may take dozens of clock cycles to reach its destination. In such a case, dividing the device into smaller dice and using high-density interconnects on a package substrate actually can be faster.³

Another concern is combining increasingly different technologies on one chip. Copper interconnects with low-k dielectrics are just the first of many new materials that will be introduced. Developing new materials for next-generation memory technologies will be quite a challenge without having to integrate memory with other technologies. In this changing environment, system-in-a-package might be preferable as an interim solution, if not the final one.

Similarities between the different technologies may allow reduction of the number of mask steps needed, but there still will be differences. Each technology might have to be altered just to make integration possible, which could degrade the performance of each. Such alterations may not be that serious, but the possibility should be examined thoroughly.

Multichip packages

In general, a multichip package is any package that contains more than one die. Multichip modules have been around for decades, mostly for low-volume, high-reliability applications; because of this the term "multichip" has become synonymous with "expensive." New, lower-cost multichip options are available for high-volume applications.

The term "multichip packaging" seems to be reserved for cases where two or more off-the-shelf dice are placed in a single package. They can be off-the-shelf parts or a chip set packaged together to save space.

One class of multichip package gaining wider acceptance is stacked-die packaging. Figure 3 shows some of the stacked-die packaging options. The simpler, wirebonded CSP versions are suitable for stacking memory, where the main concern is saving space. The scenario labeled S-MCM is used in cases where the number and arrangement of bond pads make it impractical to wirebond a three-level stack, which may occur with high I/O logic and a lower I/O memory stack.

3. There are many ways to combine dice in a single package to optimize cost and performance; most use off-the-shelf dice. (Source: Amkor Technology)

Where high die-to-die I/O density is needed, flip-chip-on-chip (FCOC) is used as denoted by FS-CSP¹ in Figure 3. Companies providing flip-chip-on-chip services include SyChip (Warren, N.J.), APACK (Hsinchu, Taiwan), IBM and Amkor (Phoenix). Where one die requires high I/O density to the substrate, such as an ASIC, the hybrid approach depicted as FS-CSP² can be used.

Other schemes for stacking dice and interconnecting them include Irvine Sensors' (Costa Mesa, Calif.) Neo-Stack and Tru-Si Technologies' (Sunnyvale, Calif.) stacked wafer-level packaging (S-WLP).

Multichip devices

Some multichip arrangements comprise a complete "unit," though not necessarily a complete system. Such "units" can be referred to as multichip devices. It is a complete processing unit, though not a complete computer. Keeping costs down usually has been the motivation for using solutions such as this.

Another example of such a subsystem is the 5.2 GHz wireless LAN front-end circuit shown in Figure 1. Gallium arsenide ICs, silicon ICs and thin-film passives were designed together as a system to improve its performance.

Another multichip package strategy that has not been used widely is partitioned silicon, the intentional separation of a single technology system into more than one die. Smaller dice yield better, and moving long global interconnects off the die and onto the package substrate can shorten their signal propagation delay. This requires adjustments to the IC's architecture, appropriately designed chip-to-chip drivers and high-density packaging technology to be successful.

On this subject, Len Schaper of the University of Arkansas said: "There are tradeoffs in how you make that decision. A lot of packages already involve the need for dense I/O connections to the chip. Take any of the latest microprocessors, and you've got a dense area array flip-chip, so your package is a pretty sophisticated part in itself. It's going to handle all of that interconnect density. And if you can do that, then it probably can handle getting from that chip to a really functional cache chip. That would be very complementary and would result in less delay than running the whole thing around on the one chip."

The design chapter of the 1999 Roadmap suggests asynchronous communication methods may be required to send signals between circuit blocks on large chips in upcoming generations. If this becomes a necessity for a particular IC, and circuit blocks communicate asynchronously, then putting those circuit blocks on different dice will not add any problems.

There are other ways to use the partitioned silicon approach to make faster systems if ICs are altered in a global optimization of the multichip device. Using a 128-bit memory bus within the package instead of a 32-bit bus, for example, would increase the bandwidth of the bus 4× and eliminate the multiplexing on the memory chips.

Also, packaging a chip set within a package can lead to simpler chip designs. Alpine Microsystems' Sam Beal said: "If you're driving 3.3 volts for external I/O, but your core voltage is 1.8, then you've got two different voltages on your IC. You've got thicker oxides and thinner oxides, and you've got to isolate the voltages. But if you're only driving 1.8 inside of the package, then all of that 3.3 could go away, potentially."

In all of these partitioned silicon examples, the ICs are altered in some way to optimize the overall device. While this allows performance and cost gains, it also is the main drawback. In addition to known good die (KGD) issues, which are considerable, the dice are not really complete until they are integrated into the multichip device. IC makers may find this too awkward to pursue unless the gains are extraordinary.

System-in-a-package

System-in-a-package is defined differently by different people, and those differences deal mostly with what is considered a system. Logic and memory in one package would be a multichip package, but without things like analog peripheral device drivers, that package does not really contain a system.

Rao Tummala, of the Georgia Institute of Technology, defines a system-in-a-package as "one package providing all the functions of systems needs of tomorrow." Those functions include digital, analog, rf, MEMS and high-bandwidth communication technology. He describes his concept of a system of tomorrow this way: "I would like to have, in my pocket, gigabit per second wireless Internet access; at the same time I could talk; at the same time I could do e-mail; and at the same time it computes." Even with maximum integration of functions on ICs, this will require a multichip solution.

One reason for seeking on-chip integration of a system would be to avoid the size of a multichip module. Multichip modules traditionally have been large packages, built for high reliability. However, many one-chip systems can end up as a very large piece of silicon that is difficult to package. Technologies under development can place multichip systems in smaller packages.

When considering a complete system, semiconductor devices are not the only things to consider. Passive devices are required to make systems work, and if an entire system is to be placed in a package, then the required passives must go in as well. This cannot be done unless they are reduced in size. A typical cellular phone is a good example, with dozens of ICs and hundreds of passive devices.

Recent work at the High Density Electronics Center at the University of Arkansas (HiDEC, Fayetteville, Ark.) is based on the premise of removing superfluous material and using three dimensions. Len Schaper, the director, said: "I think there is a 50 to 100 times improvement in volumetric efficiency of the packaging of parts per cubic inch that can be achieved in what I see as the next revolution in packaging."

4. This concept for system-in-a-package uses thin-film conductors and passives on flex along with ultrathin dice to realize a system with a minimum of "superfluous material." (Source: High Density Electronics Center, University of Arkansas)

Figure 4 shows the packaging concept developed at HiDEC to realize this volumetric efficiency.⁴ All ICs are thinned and flip-chip attached in, not just on, a build-up of flex layers with copper conductors. Those flex layers contain thin-film passive devices. Integrated heat pipes are added where necessary in the glue layers. Schaper also believes batteries can be miniaturized significantly.

Work at the Packaging Research Center at the Georgia Institute of Technology has yielded the single-layer integrated module (SLIM, Fig. 5). All chips, passives and optical components are placed within a buildup of polymer layers. Referring to the SLIM, Tummala said, "SOP, I believe, can reduce systems by almost 1000 times while simultaneously improving performance and reducing cost."

IMEC has done work along these lines, building systems such as integrated detector-amplifiers and rf modules. Components are placed in successive layers of benzocyclobutene (BCB).^5-6Toru Ishida recently presented a system-in-a-package concept under development by Matsushita Electric Industrial (Osaka, Japan)⁷, based on seamless integration for a system-in-a-package or even a system-in-a-board.

Design needs

5. The single-layer integrated module (SLIM) is designed to integrate all technologies required for upcoming systems. (Source: Packaging Research Center, Georgia Institute of Technology)

One of the main future needs for system-in-a-package technology is related to a current need for more conventional packaging: improved design tools. Current needs are forcing increased codesign of chip and package.

Designing systems-in-a-package such as the ones described above will require more sophisticated design tools than are available today. Schaper noted: "Design systems cannot keep track of all of the parasitics that you get when you start packing things at that kind of density. Those are going be key, ways to design things where the z-axis is used for something other than air." He went on to say: "So we're now able to build things that we can't design. Because we can build three-dimensional stacks with passives embedded in boards and on flex layers, but there's no good design system to handle that."

Conclusion

Though SOC integration will be the best choice in some situations, it definitely will not be best in all system integration situations. Sometimes cost will force a multichip solution; sometimes it will be performance, and sometimes technology incompatibilities. Many factors come into play in determining whether SOC is a viable choice, and many more options exist for packaging multichip systems. Though there will be pressure to integrate as much functionality on as few chips as possible, real single-chip systems will be impractical if not impossible to make in most applications. Now that chip and package are starting to be co-designed, an opportunity exists to develop capabilities for designing the system-in-a-package solutions that would cost less and perform better than system-on-a-chip solutions. •

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REFERENCES

1. 1999 International Technology Roadmap for Semiconductors.
   
2. R. R. Tummala, "SOP vs. SOC: Needs, Challenges and Status," 2000 European VLSI Packaging and Microsystem Packaging Techniques and Manufacturing Technologies Workshop, May 8-9, 2000, Cork, Ireland
   
3. E. Davidson, "Large Chip vs. MCM for a High-Performance System," IEEE Micro, July/August 1998, pp. 33-41.
   
4. L. Schaper, "Ultimate Packaging: The Limits of Density," Keynote presentation, HD International, Denver.
   
5. K. Vaesen, S. Donnay, P. Pieters, G. Carchon, W. Diels, P. Wambacq, W. DeRaedt, E. Beyne, M. Engles, I. Bolsens, "Chip-Package Co-design of a 4.7 GHz VCO," Proceedings of the 2000 International Conference on High Density Interconnect and Systems Packaging, Denver, April 25-28, 2000, p. 301-6.
   
6. J. Baliga, "MCM Has Chips in Redistribution," Semiconductor International, February 2000, p. 64.
   
7. T. Ishida, "A Vision of Electronics in the 21st Century," Proceedings of the Technical Program, Fifth Annual Pan Pacific Microelectronics Symposium, January 2000.