Diagnosing Latch-up with Backside Emission Microscopy
Thomas Kessler, Friedrich-Wilhelm Wulfert Motorola Semiconductor Products Sector, Quality, Munich, Germany Thomas Adams Hypervision Inc., Fremont Calif. -- Semiconductor International, 7/1/2000
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At a Glance | | |
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The device described here is a hyperintegration part, a microcontroller having EEPROM, its own voltage regulator, other analog circuitry and also high-voltage power output drivers. Initial testing demonstrated this device was susceptible to latch-up conditions. Under moderate electrical supply conditions, latch-up was induced in a parasitic SCR (Semiconductor Controlled Rectifier) structure formed by adjacent diffusion zones. An SCR consists of back-to-back npn and pnp transistors (vertical and lateral junctions); latch-up occurs when the amplification product of the transistors is >1. In a hyperintegration part such as this one, corrective action includes making the beta smaller by restructuring the layout or respectively moving and resizing structures to increase spacings.
The conventional approach would be to decapsulate the device and examine it from the frontside. If latch-up already had reached a destructive level, the molding compound would be charred. Removal of the molding compound from such a device would reveal the extent of the damage — often a crater in the chip's circuitry — but would give no exact information that would be useful in redesign to avoid latch-up. If the device were decapsulated before latch-up occurred, an emission microscope could be used to observe the light being emitted before and during latch-up. But, as will be explained, the location of the emitted light would not necessarily correspond to the actual location of the latch-up initiation site, and the received information would not be usable for effective redesign.
Since it is vital to obtain detailed information on which to base corrective design actions in the shortest time, a different approach was used: the backside device silicon was thinned, and rapid-sequence emission imaging of the light emitted by latch-up was carried out from the backside.
Non-linear currents do not tend to emit light only at silicon defects but also under several electrical conditions stressing the silicon and dielectrics. These include avalanche and reverse breakdown, tunneling, channel saturation, heavily forward-biased junctions and latch-up. In conventional chip designs, the faint light emitted by these effects escapes upward from the circuitry and can be detected by an emission microscope viewing the frontside of the chip. In this way the precise location of the defect site can be determined.
A common feature of more advanced designs is the presence of multiple layers of metalization. Either large areas of the silicon structures are completely covered by metal or several subsequent layers of metal inhibit the light from escaping upward. In some cases, the light does escape but only after multiple reflections off of metalization; but in many devices light emissions cannot reach the frontside at all.
Fig. 1) after a trigger current of >70 mA was driven into the chip causing latch-up. With a limited supply current, latch-up occurs but does not destroy the device. Light from the latch-up event was visible from the frontside, but the distribution of the light — namely, in two separate spots both at the edge of a large area of metalization — made it very likely the actual initiation site of latch-up was occurring under the metalization. Since the actual initiation site could not be observed from the frontside, the mechanism and exact location could not be identified conclusively, and therefore no redesign decisions could be made from this data.
To permit backside emission imaging, the backside silicon was thinned until the silicon remaining over the area of the chip circuitry had a thickness of 0.05 mm to 0.1 mm. Silicon is partly transparent to the wavelengths with energies below the bandgap emitted by the effects named above; in addition, transmission of emitted light through silicon is strongly affected by the degree of silicon doping. Heavily doped silicon transmits only a small percentage of photons emitted. Silicon thinning was accomplished by an automated system (manufactured by Hypervision Inc., Fremont, Calif.) which removes packaging material and a pre-defined thickness of silicon. The thickness of silicon that must be removed can be approximated by knowing the degree of doping, but in working with multiple samples of the same chip design practical experience dictates the thickness of remaining silicon through which emissions will be seen.
After removal of the silicon from the backside, the bottom surface of the milled silicon is polished to improve the transmission of light from an illuminator from the backside. Emission images consist of the overlay of two separate images: the light emitted by the defect (usually one or more points or areas of light) and the illuminated image showing the structure of the circuitry. The illuminator used from the backside employs IR wavelengths to which silicon is transparent. Both the silicon thinning process and the polishing process are automated to achieve speed and reproducibility.
After thinning the backside of the package to permit emission microscopy, the trigger current can be varied at will, and emission images can be made at various current levels. Since backside emission imaging is a fairly rapid procedure, the resulting images can be made at relatively short intervals — in the case of this device, probably as short as 1 sec — as the trigger current is manipulated.
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The trigger current level was then increased to >70 mA to reach latch-up condition and to record Figure 4. The picture shows the established low-resistive path between the supplies, which is indicated by the "hot spot" and allows the localization of the latch-up initiation site, which is near the lower left of the metalization area. The intensity of the light emission is much greater, and light emissions are now escaping toward the frontside from both locations seen in frontside imaging in Figure 1.
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As a result of backside emission imaging, the precise location of latch-up was found quickly and conclusively. It was very helpful to be able to show the sequence of latch-up light emissions to design and layout personnel. The chip structures were then redesigned and the diffusions zones rearranged without increasing the die size. Testing of devices from subsequent production showed a decrease in susceptibility to latch-up by a factor of ten. •
Tom Adams is a writer and consultant based in Lawrenceville, N.J. He has written extensively on semiconductor test and reliability issues. Phone: 1-609-883-5040 e-mail: teadams@earthlink.net
