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How to Reduce Plasma Damage in Sputtering Processes

Peter Ansmann and Duncan Perry Fraunhofer Institute for Solid State Technology, Munich, Germany Andreas Jaeger Metron Technology, Munich, Germany -- Semiconductor International, 6/1/2000

  
 At a Glance

The authors have investigated the effect of plasma damage caused during the sputter etch step prior to second-level aluminum metalization, which is necessary to remove the insulating aluminium oxide from the surface. They also examined the influence of key etching parameters on plasma charging and, from the results, were able to develop a new process that increased device yield by over 10%.

The plasma processing techniques necessary in the production of microelectronic devices are becoming more complex and widespread in their use. As a result of the continual shrinking of MOS device dimensions, and especially of gate oxide thickness, the allowable levels of charge created on the devices during processing also must decrease. The main reason for this charging effect (seen in all plasmas to some degree) is a non-uniform plasma; that is to say the ion and electron currents are severely unbalanced (Fig. 1).

1. Charging effects are a result of non-uniform plasmas.

To better understand the process and its effect on device parameters and yield, we undertook a study to evaluate the principle parameters in our plasma with respect to charging and oxide etch characteristics. In our case, we found that the yield dropped when devices were exposed to plasma charges >4.5 x 1011 q/cm2, either as a result of gate oxide damage (threshold voltage shift, etc.) or complete breakdown. In general, however, the allowable maximum value for plasma charge depends on many parameters, such as tool design, gate oxide thickness and pattern density.

In addition, it is not only the total amount of charge that can cause problems. The difference in magnitude of charge between different areas on integrated circuits also can result in damage and yield loss by Fowler-Nordheim pre-stressing of the gate oxide. (This is more evident as gate oxides become thinner.) The more susceptible the gate oxide is, the more important it is to have the ability to develop plasma processes that minimize plasma charging.


2. A representative map of the VPDM measurements obtained with the plasma damage monitoring (PDM) tool used in the study.

Instead of using traditional, time-consuming and very expensive antenna test structures or Charm wafers, we used a PDM (Plasma Damage Monitoring) tool manufactured by Semiconductor Diagnostics Inc. This technique measures the build-up of the deposited plasma charges during plasma processing on SiO2. With up to 6000 measured points per wafer, a map of detailed information about the charge distribution over the entire wafer can be made.


3. This surface band diagram shows an overview of all related charges and/or potentials associated with the Si/SiO2/ air/probe system.

The purpose of our study was to examine the influence of different process parameters on plasma damage (and hence yield loss) during a sputter etch step prior to second-level metallization. This step is necessary to remove the insulating Al2O3 layer that forms on aluminum during exposure to an oxygen plasma (ashing of photoresist) and normal exposure to air, which otherwise would prevent metal level-1 and level-2 contact.

Sputter etch process

We investigated the influence of all parameters for the sputtering process by a "one-variable method" as well as by a DOE (design of experiment) technique. The range in which the parameters were varied is: Ar flow from 5 to 100 sccm; rf power from 150 to 400 W; the current of the outer magnet of the magnetron from 3 to 7 A; and the current of the inner magnet from 0.75 to 5 A. For the experiments, bare silicon wafers (p-type, r = 12 V-cm) were prepared with a 5000 Å thermal oxide.


4. Sensed voltage vs. oxide charge buildup for p-type silicon with various oxide thicknesses.

The sputter etch chamber is of fairly simple construction, consisting of two principle parts, an electromagnetic source and an rf powered wafer platen (13.56 MHz), which are separated by approximately 3 cm. The magnetic field is supplied by a dual pole magnetron that operates the inner and outer coil currents on a fixed current, which can be varied in a range from 0 to 10 A. The etch process uses an inductively coupled plasma, where the wafer is the cathode and the magnetic field can be varied to sustain the plasma and achieve uniformity of etching.

The sputter pressure is completely dependent on the argon flow (between 2 and 100 sccm or 0.8 mTorr to 6 mTorr). The typical set of process parameters used for the one-variable experiment method are: argon 40 sccm (2.7 mTorr); rf power 300 W (equivalent dc-bias 350 V); inner coil current 3 A; and outer coil current 7 A.

Plasma damage monitoring


5. At low argon gas flows, with an outer/inner coil current of 3/7 A, the areas with maximum charge densities are reduced compared to those with high argon flows.

All wafers were measured with the MC/PDM/SPV 3030 tool from SDI. A representative wafer map of the VPDM measurement is shown in Fig. 2. The buildup of plasma charge on the oxide is measured with a non-contact, surface potential sensor.1,2 The quantity of the plasma charge can be expressed in the PDM voltage VPDM and the plasma charge QP itself. The surface band diagram of the system silicon/silicon dioxide/air/probe shows an overview of all related charges and/or potentials (Fig. 3). VPDM is the change of the silicon surface potential at the surface, caused by the plasma charge QP, and is described by the equation:

&nbsp

Where DVOX is the change of the oxide barrier voltage and DVSis the change of the silicon surface barrier voltage. VS can be measured with a special sensor under strong illumination (e.g., with a GaAs laser), and a distinction of DVOX and DVScan be made.4


6. The influence of rf power on charging is very small.

The change of the silicon surface barrier voltage VS is a complex function of the plasma charge QP, the surface condition, the oxide charges and the silicon doping. As with normal cases, where thick oxides exhibit VOX > VS, the change of the surface barrier voltage can be neglected for oxides >1000 Å (Fig. 4)1-4 and QP can be simply expressed as:

&nbsp

where QP is the plasma charge in [q/cm2], dOX is the oxide thickness in Å, and eOX is the permittivity of the oxide.1 As seen in Fig. 4, for thin silicon dioxide, two measurements for VOX and VS are necessary or the measurements will be done under strong illumination. A typical charge range in which plasma damage can occur is around 4.5 x 1011 q/cm2 (shaded area in Fig. 4).

The measurement for DVS is not necessary for thick oxides, as previously mentioned. The PDM tool2 used in this study measured VPDM with a non-contact, surface potential sensor (modified Kelvin probe) that detects an ac signal generated by an oscillating shutter between the capacitively coupled reference electrode and the wafer. The other contact is the large wafer chuck capacitance. The system measured the difference of the surface potential between the electrode and the wafer surface. The measurement was performed with a vibration frequency of 1 kHz (shutter) and a sensitivity of 1 mV.

Results


7. The best results were obtained using an inner coil current of 5 A.

By varying argon flow, coil currents of the magnetron and rf power, we saw that rf power and argon flow have only a small influence on plasma damage.

At low argon gas flows, with an outer/inner coil current of 3/7 A (Fig. 5), the areas with maximum charge densities are reduced compared to those found with high argon flows.

The maximum charge densities found with argon flows from 5 to 40 sccm show values of around 6.5 × 1011 q/cm2. The maximum charge densities were found between 60 and 100 sccm, exhibiting values around 8.5 × 1011 q/cm2. Independent of the argon flow, around 55% of the wafer area is always below 3 × 1011 q/cm2. It is shown in Fig. 5 that only argon flows of 40 sccm or lower can reduce the charging effect.


8. Charge density can be effectively decreased by keeping the outer coil current below 4 A.

To study the dependence of the areas with a high charge density, tests were designed to look at how rf power influences the charging behavior. We found that the influence of the rf power is very small (Fig. 6). We used processes with high rf power (300 W) because the interpretation shows only a small decrease of the charge density with higher rf power.

To clarify the influence of the magnet coils (outer coil and inner coil) of the magnetron, we conducted a DOE for the coil current in addition to the one-variable experiment. The rf power was 300 W, and the argon flow was kept at 40 sccm. The inner coil current was first changed from 3 to 5 A, with a fixed outer coil current of 3 A. As seen in Fig. 7, the best results were obtained using an inner coil current of 5 A.

Based on these results, we then changed the outer coil current from 3 to 7 A, with a fixed inner coil current of 3 A. The results (Fig. 8) show that the charge density can be effectively decreased when outer coil currents are 4 A or less. The best results were obtained using an outer coil current of 4 A.


9. Reducing the ratio of inner to outer coil current improves etching behavior (inner/ outer current ratio of 0.42).

However, using SiO2 as a sputtering surface, the parameters that exhibit low levels of plasma charging (inner and outer coil currents of 3 A and 5 A, respectively) exhibit an extremely high non-uniform etching rate. As shown in Fig. 9, an improvement of the etching behavior can be achieved by reducing the ratio of inner to outer coil current.

Since the amount of plasma charging is influenced mainly by the outer coil current and the non-uniformity of etching is determined by the ratio of the coil currents, it was necessary to further reduce the coil currents. The best non-uniformity will be found for an inner to outer coil current ratio of 0.42 (inner to outer coil current = 3/7).


10. Influence of inner and outer coil currents on charging.

To verify the dependence of the coil current ratio to the uniformity, two additional experiments were made with a ratio of 0.42 (inner to outer coil current = 1.5/3.5 and 0.75/1.75). As expected, the plasma charging is further decreased compared to the coil current ratio 3/7, although non-uniformity is somewhat higher (though still in an acceptable range).

For further investigations of the influence of the magnetron, we calculated the influence of inner coil current versus outer coil current on the charging behavior (Fig. 10).

It can be seen that only for small coil currents can high yield be reached (Fig. 10). Using test wafers, we could verify all of our results (Fig. 11). The comparison of Figs. 10 and 11 shows a high conformity between charging and actual yield loss. The small differences are mostly caused by the reduced amount of test wafers used to calculate the yield loss shown in Fig. 11.


11. Yield loss dependence on inner/outer currents using test wafers.

Conclusion

Using a PDM tool, we were able to quickly get information about the influence of plasma process parameters on plasma damage. This resulted in an increase of the yield of the devices. The influence of the magnetron on plasma damage could be successfully reduced by lowering the coil currents. A lowered magnetic field strength directly influences the ionization rate of the plasma, which results in a reduced charging behavior. •


REFERENCES
  1. A. Hoff, T. Esry and K. Nauka, "Monitoring Plasma Damage: A Real Time, Non-Contact Approach," Solid State Technology, July 1996.
  2. J. Lagowski, A. Hoff, L. Jastrzebski, P. Edelman and T.Esry, "A Novel Method For Studying Degradation Related to Plasma Processing of Silicon Wafers," Materials Research Society Spring Meeting, April 1996.
  3. K. Nauka, J. Kruger, W. Dixon, W. Greene, B. Langley and J.Lagowski, "Monitoring of Dielectric Charges Introduced by Plasma Processing with Surface Photovoltage and Contact Potential Difference Measurement," INFOS1995 Symposium in Grenoble
  4. J. Lagowski and P. Edelmann, "Contact Potential Difference Methods for Full Wafer Characterisation of Oxidized Silicon," DRIP VII. 7th International Conference of Defects Recognition and Image Processing in Semiconductors, Sept. 1997, Templin.

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