Low-k Dielectrics: Will Spin-On or CVD Prevail?

Laura Peters, Senior Editor -- Semiconductor International, 6/1/2000

One key advantage to a CVD-based low-k approach is the reuse of existing toolsets. (Photo of Sequel tool courtesy of Novellus Systems)

Proponents of CVD approaches, most notably carbon-doped siloxanes (OSGs) with k ranging to below 2.5, claim reuse of existing toolsets and simpler integration due to the silicon dioxide-like structure of CVD siloxanes. OSGs also represent the most limited departure from the standard SiO₂ dielectric. Alternatively, manufacturers of spin-on materials and spin-on dielectric (SOD) tracks contend better extendibility to future generations, especially in the sub-2.5 range when porous low-k materials likely will be used. Today, porous versions of many low-k spin-ons are available for testing, whereas porous CVD low-k materials have yet to be demonstrated. Some spin-on materials also may require a smaller pore volume to attain ultralow k(k<2.2) than CVD films, which may contribute to higher mechanical integrity, better film stability and easier integration. Companies on both sides claim about 80% of the overall low-k interlevel dielectric (ILD) market. Both sides also tout a lower cost-of-ownership.

"The battle between CVD and SOD at k = 2.8 is staged by the desire to extend CVD tool sets for one more technology node, on one hand, versus the extendibility of new SOD materials and process integration schemes for multiple generations," said Dr. Ajit Rode, senior vice president and general manager of FSI International's SOD Operations (Fremont, Calif.). "The key is to provide a SOD solution that can be extended for multiple generations and can process both 200 mm and 300 mm wafers on the same equipment."

The CVD versus spin-on argument is further influenced by business approach. For instance, CVD suppliers can, in many cases, provide an integrated solution to the customer, the starting point from which the device manufacturer's process is developed. "The foundries are in the midst of a transition from being fast followers to leading-edge companies," explained Peter Nunan, vice president of strategic alliances at KLA-Tencor. "Given the tight labor market for engineering talent in Taiwan, foundries need to rely on vendors for low-k solutions that have been well characterized and can be easily introduced into production." For this reason, foundries such as TSMC and UMC, both of whom project copper capability by the end of this year, might be more likely to choose a CVD low-k process over a spin-on process. This theory is confounded, however, by UMC's recent technology alliance with IBM.

Low-k today

State-of-the-art effective k values in pilot production today are around 3.0, typically attained by combining a low-k ILD of 2.7-2.8 with a silicon carbide (SiC) based dielectric barrier, capping or hard mask layers with a k around 4.5. IBM is attaining a 3.0 effective k using SiLK ILD (k=2.65) with SiC-based barriers and hard mask. TI is combining Applied Materials'Black Diamond ILD (2.7) and BLOk SiC film for k around 3.0.

Taking an alternative approach, LSI Logic is combining Trikon's FlowFill CVD film (k=2.8) with subtractive aluminum metallization to attain k=3.1. "We compared use of copper with conventional dielectrics versus aluminum with low-k, and found you'd get about the same amount of performance benefits with aluminum/low-k without the high risk associated with switching to copper damascene and the greater amount of capital investment," stated Rich Schinella, vice president of research and development at LSI Logic (San Jose, Calif.). "We were most concerned about the reliability of the devices and defect density, so we began testing those from the beginning," he said. LSI will first use FlowFill low-k at the upper levels in its 0.18 µm generation, migrating to all metal levels in subsequent 0.13 and 0.10 µm generations using the Planar platform.

"There's a lot of facets to incorporating a low-k material into an interconnect system," Schinella explained. "Part of it is the material itself and its performance with respect to thermal stability, permeability, moisture absorption, chemical tolerance and hardness." He continued, "Then you need to be able to process the material without altering its structure." Depending on the low-k material, a variety of plasma treatments, thermal treatments or other steps may be added to stabilize the film during processing, which becomes a large part of a chip manufacturer's expertise in bringing low-k materials into a manufacturing environment.

A question of timing

Overall, implementation of low-k dielectrics has been stalled drastically, as indicated by changes to the SIA Semiconductor Industry Roadmap from 1997 to 1999 (Table 1). It also is quite possible the expected change from a k range of 2.7-3.5 to <1.5 (k_eff=1.5-2.0) will be stretched beyond the 70 nm generation due to a dramatic increase in integration challenges for materials with dielectric constants below 2.0.

Table 1. SIA Roadmap
1997
Year of first product	1997	1999	2001	2003	2006	2009	2012
Shipment technology node	250 nm	180 nm	150 nm	130 nm	100 nm	70 nm	50 nm
Interlevel metal insulator effective k	3.0-4.1	2.5-3.0	2.0-2.5	1.5-2.0	1.5-2.0	<1.5	<1.5
1999
Year of first product		1999	2001	2002	2005	2008	2011
Shipment technology node		180 nm	150 nm	130 nm	100 nm	70 nm	50 nm
Interlevel metal insulator effective k		3.5-4.0	2.7-3.5	2.7-3.5	1.6-2.2	<1.5	<1.5
2000?
Year of first product			2001	2003	2005	2007	2009	2011
Shipment technology node			180 nm	150 nm	130 nm	100 nm	70 nm	50 nm
Interlevel metal insulator effective k			3.5-4.0	2.7-3.5	2.7-3.5	2.2-2.7	2.2-2.7	1.6-2.2

The effective dielectric constant required at each device generation was pushed out from 1997 to 1999. The 2000 edition could extend the use of k=2.4-3.3 (keff=2.7-3.5) materials due to integration challenges.

"The most immediate challenge for the industry is ramping production at 0.18 µm," said Andy Noakes, CVD products marketing manager at Trikon Technologies (Santa Clara, Calif.). "I think there's really two choices — copper first or low-k first. The most cost-effective gain occurs with aluminium/low-k, particularly if you can implement a k < 3.0. Hybrid structures with aluminum/low-k for the lower metal layers and copper at the very top levels will give manufacturers the ability to ship 0.15/0.13 µm product in the short to medium term, stalling the significant challenge of integrating copper and low-k."

Reasons for the low-k delay include the lack of a clear "winner" among various candidates, complex integration issues,¹ the current two-year timeframe between technology nodes (less time to prove new materials), and perhaps limited funding during an industry downturn. However, the most frequently cited reason for the delay stems from the nearly impossible task of making two large leaps — from aluminum to copper interconnects and from SiO₂ to low-k dielectrics — simultaneously. For some companies, copper was the easier change, despite challenges with damascene structures, the switch to electroplating tools and copper CMP. Still, others are minimizing their risks by combining aluminum and low-k materials, "which probably represents about 30% of the population at this time," estimated Farhad Moghadam, corporate vice president of the Dielectric Systems and Modules Product Group at Applied Materials (Santa Clara, Calif.). Despite the different approaches, it seems the time has come for low-k implementation, some at the mature 0.18 µm generation and others beginning at the 0.13 µm generation, with first processes for the latter to be frozen by the end of this year.

Low-k performance

A recent customer survey from Lam Research Corp. (Fremont, Calif.) revealed some of the most pertinent concerns of people implementing copper and low-k dielectrics (Fig. 1). The survey pointed to problems of polishing copper over low-k materials, post-CMP cleaning, removal of residue from vias, maintaining dimensions laterally and vertically, and ensuring copper film quality and productivity. The survey of 20 device manufacturers worldwide also indicated etching-specific concerns such as selectivity control, RIE lag for a timed trench etch (where the etch stop is eliminated), and device damage from the etch process. Finally, questions linger over which layers should be copper, the effectiveness of the metal barrier and selecting the right resist stripping process.

1. Leading integration concerns with copper dual-damascene structures include copper fill quality, CMP erosion and defectivity, dimensional control and via integrity. (Source: Lam Research)

All low-k CVD and spin-on materials have strengths and weaknesses. Most inorganic approaches attempt to mimic the properties of SiO₂, while adding carbon, typically in the form of methyl (-CH₃) groups, to reduce the density of the film structure; this leads to lower dielectric constant. Important low-k film properties include thickness and uniformity, dielectric constant, refractive index, adhesion, chemical resistance, thermal stability, pore size and distribution, coefficient of thermal expansion, glass transition temperature, film stress, and its copper diffusion coefficient.² These properties and others each have analytical procedures to test film properties through development and production sampling. Adhesion is particularly key, especially for organic spin-on materials that often do not adhere well to standard CVD oxide and nitride films, or barrier metals including Ti, TiN, Ta and TaN. The potential for via poisoning comes from etching and resist removal. The etch process has to be optimized for profile control and, importantly, zero damage. The stripping process replaces the traditional oxidizing chemistry with a hydrogen-based reducing chemistry.

Because all low-k films are less dense than SiO₂, they must be formulated to withstand wire bonding and CMP. "Without the necessary mechanical properties, some low-k materials may dictate the use of BGA bonding over wire bonding, or expensive ceramic packages rather than plastic packages," said Drs. Wilbert van den Hoek of Novellus Systems (San Jose, Calif.). Through process optimization, we've been able to dramatically improve the hardness of our 2.7 Coral material, allowing it to be used in standard plastic packages," he said.

In CMP, adherence to underlayers is key as the process can cause deformation. "The biggest challenge in copper CMP is the balance between underpolish, which leaves residue and leads to shorting, and overpolish, which erodes and dishes features," explained Nunan. "Because the CMP process window has not been well characterized yet for these low-k films." To increase durability, a capping layer can be used, but a lower-k film such as SiC is preferred rather than silicon nitride that will increase the effective k value. Polishing SiC layers is more difficult because dishing and erosion in densely patterned areas is more likely than in the blanket film areas. "Currently, copper CMP is very engineering-intensive," said Nunan.

2. Using low-k between metal lines but not at the via level improves the mechanical strength and reliability of the structure at the expense of manufacturing complexity.

One way of circumventing a low-k material's lack of mechanical strength is to implement it only at the line levels, using SiO₂ at the via levels. Beyond firming up the structure, this "embedded" approach (Fig. 2) can reduce moisture absorption, prevent via poisoning, and allow the fab to keep conventional dry etch and cleaning process for the vias. The embedded structure also makes for a more compatible CMP process, while allowing a company to learn from gradual integration of the low-k material. However, it seems few companies will take this approach due to the added complexity of processing and cost associated with maintaining two ILD processes. "Probably 80% of the benefit is gained by incorporating low-k material at the line level, so an embedded approach makes sense; but we're finding customers prefer to deposit one film for the trench and via, and that ties into eliminating the intermediate etch stop," explained van den Hoek.

Eliminating the intermediate etch stop requires precise metrology to identify etch depth along with maintenance of the etch characteristics delivered with a traditional etch. For instance, it may be difficult to maintain a flat etch bottom with the timed etch, possibly resulting in trenching in the corners where the metal diffusion barrier is deposited. "There's a tradeoff between pushing barrier technology to the limits versus the cost savings and capacitance reduction associated with not having the intermediate etch stop," said van den Hoek.

Before moving to low-k dielectrics, (k < 3.0), two materials extended the k value below that of
SiO₂ (thermal, k=3.9, CVD, k=4.1-4.2), fluorinated silicate glass (FSG) and hydrogen silsesquioxane (HSQ). FSG, despite stabilization problems that cause barrier metal interaction and reliability issues, is extending the use of PECVD oxide processes in both subtractive aluminum and copper damascene interconnects. HSQ was first implemented in DRAM and other devices, not because of its low dielectric constant (2.9) but to simplify and reduce the cost of processing. Since its early use, HSQ has gradually gained acceptance as a low-k spin-on material. Commercially offered as Dow Corning's Flowable Oxide (FOx), some customers have run into cracking issues with the material. "More times than not, when we saw cracking problems in our guaranteed thickness range, it could be traced to a metal etch that was re-entrant or undercut in some way," said Mark Loboda of Dow Corning (Midland, Mich.).

FSG solutions for subtractive aluminum are different from the copper damascene FSG, as explained by Moghadam. "For gapfill, the sputter component bombards the film, breaking the bonds and making the film less stable. As a result, we can obtain higher fluorine concentration in damascene applications, providing an even lower dielectric constant of 0.2 to 0.3."

The crucial k=2.8 node

3. Integrated SiLK low-k material in a copper dual-damascene interconnect using SiC base and top layers. ( Source: IBM/Dow Chemical)

Table 2 summarizes some of the leading low-k dielectric candidates. Despite connotations in the name, SiLK (Fig. 3) is a hydrocarbon that does not contain silicon. IBM will be using the film at most metal layers in its 0.13 µm ASIC process. The implication in speed gain is reflected in a 30%-40% lower total capacitance (Fig. 4), depending on the influence and thickness of barrier and etch stop materials. SiLK competes with FLARE and HOSP SODs from Honeywell (Sunnyvale, Calif.). Some SODs require precise control of temperature, humidity and sometimes oxygen levels during spin coating, and an optimized curing process. The controlled environment during coating is crucial because siloxane or silicon polymers react readily with water and are sensitive to changes in temperature and humidity. Manufacturers of spin-on dielectric (SOD) coaters include Dainippon Screen (DNS, Tokyo), Tokyo Electron Ltd. (TEL, Austin, Texas), FSI International, Semix (Fremont, Calif.) and SVG (San Jose, Calif.). Each company has optimized the coating and curing modules specifically for SODs, making them significantly different from the photoresist tracks on which they originally were based.

Table 2. Low-k Dielectric Candidates
Material	Dielectric constant	Deposition method
	Low-k materials
Polyimides	3.0-3.6	Spin-on
Spin-on glasses	2.7-3.1	Spin-on
Fluorinated polyimides	2.6-2.9	Spin-on
DLC (diamond-like carbon)	2.8-3.0	CVD
Poly(arylene ethers)	2.6-2.9	Spin-on
Poly(arylenes)	2.6-2.8	Spin-on
Cyclotenes	2.6-2.8	Spin-on
Parylene N	2.6-2.8	CVD
Poly(norbornenes)	2.5-2.7	Spin-on
Polyimide-SSQ hybrids	2.7-3.0	Spin-on
Alkyl-silanes/N2O	2.4-2.7	CVD
	Ultralow k
Teflon-AF	1.9-2.1	Spin-on
Teflon microemulsion	1.9-2.1	Spin-on
	Porous dielectrics
Polyimide nanofoams	2.2	Spin-on
Silica aerogels	1.1-2.2	Spin-on
Silica xerogels	1.5-2.2	Spin-on
Mesoporous silica	1.9-2.2	Spin-on
(Source:IBM)

Important to SOD performance is the quantitative dispense of SODs, an often overlooked aspect of the process, according to Josh Golden, senior scientist at Microbar (Sunnyvale, Calif.). "Due to the high cost(>$2000/liter) and potential sensitivity of some spin-on formulations to temperature, moisture and oxygen, materials management could play a linchpin' role in the successful commercial integration of spin-on dielectrics," said Golden.

Many track system and SOD material suppliers are providing integrated solutions, a pivotal service in this industry. "Our customers want the flexibility to choose the toolsets they are comfortable with and implement our materials on their toolsets with the best cost-of-ownership solutions," explained Mike Thomas, chief technology officer of Honeywell. "We are investing over $45 million to build a complete integration facility in Silicon Valley to prove our materials can provide the enabling technology and extendibility needed for low-k interlevel dielectrics." Honeywell soon will demonstrate how inorganic and organic SOD stacks can enable the extension of effective dielectric constant to the 2.0 regime. This can be done, according to Thomas, with no penalty in k value due to intermediate layers. Also along the lines of integration, Robert Crowell of TEL said, "Our company's strategy is to furnish the customer with an integration package including critical SOD process parameters, SOD process recipes, etching and cleaning recipes."

4. In principle, SiLK low-k material (k=2.65) can afford an overall 40% reduction in total capacitance compared to SiO 2 . ( Source: Dow Chemical )

Etching organic films requires careful etching of the hard mask, resist strip, then etching of the low-k film. Depending on the film, a wet chemistry or proprietary dry chemistry may be used to remove the resist. The etcher should have the flexibility to accommodate different damascene structures, integration schemes, and films including inorganic and organic ARCs, different resists, oxynitrides, nitrides and oxides and SiC-based films. "One key to coping with all the different films and selectivity differences is having a high bias so one can go to higher polymer forming chemistries," explained Adrian Kiermasz of Lam Research. "The second is low residence time so you can quickly change various gases and not have the memory effect in the chamber." To attain this, and to eliminate device damage, Lam has gone from an HDP etcher to a capacitively coupled system for low-k processes.

Carbon-doped siloxanes, also termed organosilicate glass (OSG), can be deposited by CVD or plasma-enhanced CVD, using a variety of precursors including methylsilane, dimethylsilane, trimethylsilane or tetramethylsilane. As one might imagine, precursors with more methyl groups are capable of incorporating more carbon into the film, though the compounds also are more difficult to dissociate. "Tetramethylsilane deposition rates are about 25% slower than trimethylsilane's because it takes more energy to dissociate the tetramethyl molecule," explained Loboda. Another key difference lies in the delivery system — a gas for trimethylsilane and a liquid for tetramethylsilane. Manufacturers of OSG CVD systems include Applied Materials, ASM America (Phoenix), Novellus and Trikon Technologies.

OSG films recently have been improved for better hardness and manufacturability. Moghadam noted that Black Diamond was validated for sub-0.18 µm devices by industry consortium International SEMATECH. "We have gone from a cool process to a hot process, allowing us to eliminate the post-deposition furnace cure while positively influencing film hardness and surface roughness," said Moghadam. He added that Applied has driven down the cost of processing to have a similar cost-of-ownership to that of TEOS PECVD.

One downside to using OSG films is the possibility of DUV photoresist poisoning if the OSG contains any nitrogen in the film. There are various "fixes" available to prevent this resist footing, such as the use of a bottom antireflective coating (BARC) layer, spin-on or CVD, or treating the low-k film in a nitrous oxide plasma. Equipment companies and device manufacturers also are exploring use of alternative oxidizers to break the film precursor, other than NO or N₂O. Alternatively, the ARC can be a composite stack of oxynitride with oxide on top, preventing a nitrogen-containing interface with the DUV resist.

Perhaps the most pivotal development in low-k processing is the silicon carbide-based dielectric barrier film, with a k value around 4.5, which can replace nitride barrier and etch stops. Both OSG and SiC-based films can be deposited using tetramethylsilane (Table 3). A joint development between Dow Corning and Applied Materials resulted in the first organosilicon process for a SiC dielectric with low leakage.^3,4

Table 3. CVD Film Properties Using Tetramethylsilane
Property	a-SiC:H	Carbon-doped SiOx and a-SiCO:H
Process temperature	300-400°C	0-400°C
Oxygen source	-	N2 or H2O2
Oxygen content	-	18-30atom%
Carbon content	30-40atom%	12-40atom%
Hydrogen content	25-40atom%	10-30atom%
Equivalent bulk density	1.6-1.8 g/cm3	1.3-1.5 g/cm3
Relative dielectric constant, k	4.0-5.5	2.5-3.0
Leakage current density @0.5 MV/cm	10-10 A/cm2	<10-10 A/cm2
Breakdown field @ 10-3 A/cm2	>2.5 MV/cm	2-8 MV/cm
Film stress	<100 MPa compressive	30-100 MPa tensile
(Source:Dow Corning)

The change to SiC barriers and etch stops alone provides such significant benefits that some device manufacturers are choosing to use carbide films with undoped SiO₂ (USG) or even FSG films. Interestingly, however, companies tend to investigate the ILD films first, and upon seeing the impact of the nitride barrier film, replace it. "Our low-k Coral film adheres well to the carbide film, which provides higher etch selectivity and lower k to give an effective dielectric constant of 3.0," claimed Novellus' van den Hoek. For instance, UMC is attaining a k value of 3.0 using Coral and SiC as barrier and etch stop (Fig. 5). Van den Hoek added, "For some of our customers, this performance is adequate for 0.1 micron technology."

5. Transmission Electron Micrograph of 3-level metal copper dual-damascene using low-k Coral SiOC CVD as the line and via dielectric with low-k (k=4.3) SiC dielectric barriers and etch stops. (Source: UMC)

Integration with carbide films also implies a need for tool platform flexibility. Without breaking vacuum, a dual-damascene approach is best served by a platform that can process silane oxides, TEOS oxides, oxynitrides, nitrides, silicon carbide and OSG, or even chambers that can deposit all these films in a development environment.

Trikon Technologies uses a thermal CVD process with methylsilane and hydrogen peroxide (H₂O₂) to create FlowFill CVD films for aluminum gapfill (Fig. 6) or copper damascene structures with a k of 2.8. For gapfill, the sequence is typically a plasma-deposited base layer, a low-temperature flow layer and an in situ cure step. The FlowFill layer can be deposited thicker (to > 1.5 µm) with a modified cure step allowing a simple extension to timed etch damascene structures using the same hardward and tool platform.

6. Low-k Flowfill CVD with aluminum lines and W-plug is processed using low-k at both the via and line levels. (Source: LSI Logic)

Whichever low-k approach is chosen at a k value around 2.8, the effective dielectric constant will be the complex result of interconnect design, choice of barrier layer, use of etch stops and other factors. Certainly the change from nitride barriers to silicon carbide-based barriers will significantly influence the k value even before the low-k ILD is introduced (Fig. 7).

Porous low-k films

Though many companies speak of porous low-k films as the natural successor to today's OSGs and spin-on organic films, porous materials have yet to be proven in actual devices. However, in this area, SOD materials are ahead with, for instance, Honeywell's Nanoglass porous silica film, originally developed in 1996. And, though porous low-k spin-ons offer the only option today, CVD companies certainly have time to develop a CVD film with a porous matrix between now and 2005, when they first will be needed. "The question you really have to ask is how low can k go before the film becomes mechanically useless," said Dow Corning's Loboda. "To get the industry into the k of 2 regime will take a paradigm shift in metallization, dielectrics, etching, and the whole way multilevel interconnects are manufactured," he said.

7. The SiC-based dielectric barrier impacts the effective k value much less dramatically than the traditional nitride film. (Source: Applied Materials)

One further change may be away from the via-first damascene approach, the most common scheme used today. "With a porous material, you cannot do via first and trench next because after you etch the via and begin etching the trench, you are going to have problems with the material absorbing the resist into the sidewalls," explained Moghadam.

Other spin-on porous materials include porous SiLK from Dow Chemical (Midland, Mich.), porous versions of FLARE and HOSP from Honeywell, and PolyELK and MesoELK from Schumacher (Carlsbad, Calif.). Another key advantage is that less porosity may be needed for the spin-ons. "If you don't start with a low k value, you're never going to get to a k of 2.0 because the toughness of the material goes to zero at high porosity," said Mark McClear of Dow Chemical. The only non-porous ultralow-k films are a PTFE spin-on film offered by W.L. Gore (Elkton, Md.) and a thermal CVD PTFE film first developed by Watkins-Johnson, now SVG Thermco Group, with precursor from DuPont Electronic Gases Group (Wilmington, Del.).

Conclusions

Despite the slowed implementation of low-k dielectrics, it appears their time has come with major announcements from IBM, Texas Instruments and LSI Logic. The spin-on versus CVD debate will continue as companies determine their integration strategies and the low-k implementation path that best suits the needs of their devices. Until then, organic spin-on materials such as SiLK are entering first production along with OSG films. As with most choices in the industry, selection of a low-k material is largely a technical one, though cost-of-ownership will have to be driven down in each case before manufacturing with the films is considered worthwhile. "The timeline for low-k will probably slip because of the exponential demand to get product out the door," said KLA-Tencor's Nunan. At the same time, 300 mm likely will be postponed to allow companies to meet existing demand for 0.25 and 0.18 µm devices. •

---

REFERENCES

1. L. Peters, "Solving the Integration Challenges of Low-k Dielectrics," Semiconductor International, Nov. 1999, p.56.
   
2. P. Nunan, "The Challenge of Low k, Issues and Considerations for Accelerated Performance," Yield Management Solutions, Spring 2000, p. 17.
   
3. P. Xu, et al, "BLOk - A Low-k Dielectric Barrier/Etch Stop Film for Copper Damascene Applications," Proc. 1999 IEEE Int'l Interconnect Technology Conf., p.109.
   
4. M.J. Loboda, "New Solutions for Intermetal Dielectrics Using Trimethylsilane-Based PECVD Processes," Microelectronics Engineering, Vol. 50, 2000, p.15.
   

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